CP3BT23_14 Datasheet, PDF (19/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
L
The Low bit indicates the result of the last comparison operation, with the operands interpreted
as unsigned integers.
0 – Second operand greater than or equal to first operand.
1 – Second operand less than first operand.
U
The User Mode bit controls whether the CPU is in user or supervisor mode. In supervisor mode,
the SP register is used for stack operations. In user mode, the USP register is used instead.
User mode is entered by executing the Jump USR instruction. When an exception is taken, the
exception handler automatically begins execution in supervisor mode. The USP register is
accessible using the Load Processor Register (LPR/LPRD) instruction in supervisor mode. In
user mode, an attempt to access the USP register generates a UND trap.
0 – CPU is executing in supervisor mode.
1 – CPU is executing in user mode.
F
The Flag bit is a general condition flag for signalling exception conditions or distinguishing the
results of an instruction, among other thing uses. For example, integer arithmetic instructions
use the F bit to indicate an overflow condition after an addition or subtraction operation.
Z
The Zero bit is used by comparison operations. In a comparison of integers, the Z bit is set if the
two operands are equal. If the operands are unequal, the Z bit is cleared.
0 – Source and destination operands unequal.
1 – Source and destination operands equal.
N
The Negative bit indicates the result of the last comparison operation, with the operands
interpreted as signed integers.
0 – Second operand greater than or equal to first operand.
1 – Second operand less than first operand.
E
The Local Maskable Interrupt Enable bit enables or disables maskable interrupts. If this bit and
the Global Maskable Interrupt Enable (I) bit are both set, all interrupts are enabled. If either of
these bits is clear, only the nonmaskable interrupt is enabled. The E bit is set by the Enable
Interrupts (EI) instruction and cleared by the Disable Interrupts (DI) instruction.
0 – Maskable interrupts disabled.
1 – Maskable interrupts enabled.
P
The Trace Trap Pending bit is used together with the Trace (T) bit to prevent a Trace (TRC) trap
from occurring more than once for one instruction. At the beginning of the execution of an
instruction, the state of the T bit is copied into the P bit. If the P bit remains set at the end of the
instruction execution, the TRC trap is taken.
0 – No trace trap pending.
1 – Trace trap pending.
I
The Global Maskable Interrupt Enable bit is used to enable or disable maskable interrupts. If this
bit and the Local Maskable Interrupt Enable (E) bit are both set, all maskable interrupts are
taken. If either bit is clear, only the non-maskable interrupt is taken. Unlike the E bit, the I bit is
automatically cleared when an interrupt occurs and automatically set upon completion of an
interrupt handler.
0 – Maskable interrupts disabled.
1 – Maskable interrupts enabled.
Bits Z, C, L, N, and F of the PSR are referenced from assembly language by the condition code in
conditional branch instructions. A conditional branch instruction may cause a branch in program execution,
based on the value of one or more of these PSR bits. For example, one of the Bcond instructions, BEQ
(Branch EQual), causes a branch if the PSR.Z bit is set.
On reset, bits 0 through 11 of the PSR are cleared, except for the PSR.E bit, which is set. On warm reset,
the values of each bit before reset are copied into the R2 general-purpose register. Bits 4 and 8 of the
PSR have a constant value of 0. Bits 12 through 15 are reserved. In general, status bits are modified only
by specific instructions. Otherwise, status bits maintain their values throughout instructions which do not
implicitly affect them.
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