CP3BT23_14 Datasheet, PDF (51/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

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CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
9.2 TRANSFER TYPES
The DMAC uses two data transfer modes, Direct (Flyby) and Indirect (Memory-to-Memory). The choice of
mode depends on the required bus performance and whether direct mode is available for the transfer.
Indirect mode must be used when the source and destination have differing bus widths, when both the
source and destination are in memory, and when the destination does not support direct mode.
9.2.1 Direct (Flyby) Transfers
In direct mode each data item is transferred using a single bus cycle, without reading the data into the
DMAC. It provides the fastest transfer rate, but it requires identical source and destination bus widths. The
DMAC cannot use Direct cycles between two memory devices. One of the devices must be an I/O device
that supports the Direct (Flyby) mechanism, as shown in Figure 9-1.
Bus State
T1
T2
Tidle
T1
CLK
DMRQ[3:0]
ADDR
ADCA
DMACK[3:0]
DS005
Figure 9-1. Direct DMA Cycle Followed by a CPU Cycle
Direct mode supports two bus policies: intermittent and continuous. In intermittent mode, the DMAC gives
bus mastership back to the CPU after every cycle. In continuous mode, the DMAC remains bus master
until the transfer is completed. The maximum bus throughput in intermittent mode is one transfer for every
three System Clock cycles. The maximum bus throughput in continuous mode is one transfer for every
clock cycle.
The I/O device which made the DMA request is called the implied I/O device. The other device can be
either memory or another I/O device, and is called the addressed device.
Because only one address is required in direct mode, this address is taken from the corresponding
ADCAn counter. The DMAC channel generates either a read or a write bus cycle, as controlled by the
DMACNTLn.DIR bit.
When the DMACNTLn.DIR bit is clear, a read bus cycle from the addressed device is performed, and the
data is written to the implied I/O device. When the DMACNTLn.DIR bit is set, a write bus cycle to the
addressed device is performed, and the data is read from the implied I/O device.
The configuration of either address freeze or address update (increment or decrement) is independent of
the number of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All
these can be configured for each channel by programming the appropriate control register.
Whether 8 or 16 bits are transferred in each cycle is selected by the DMACNTLn.TCS register bit. After
the data item has been transferred, the BLTCn counter is decremented by one. The ADCAn counter is
updated according to the INCA and ADA fields in the DMACNTLn register.
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