CP3BT23_14 Datasheet, PDF (166/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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For these minimum BTL settings, four CAN bit times take 32 clock cycles.
The following is an example that assumes typical case:
• Minimum BTL settings
• Reception and copy of a remote frame
• Update of one buffer from TX_RTR
• Schedule of one buffer from transmit
As outlined in Table 18-22, the copy process, update, and scheduling the next transmission gives a total
of 17 + 3 + 2 = 22 clock cycles. Therefore under these conditions there is no timing restriction.
The following example assumes the worst case:
• Minimum BTL settings
• Reception and copy of a remote frame
• Update of the 14 remaining buffers from TX_RTR
• Schedule of one buffer for transmit
All these actions in total require 17 + (14 × 3) + 2 = 61 clock cycles to be executed by the CAN module.
This leads to the limitation of the Bit Time Logic of 61 / 4 = 15.25 clock cycles per CAN bit as a minimum,
resulting in the minimum clock frequencies listed below. (The frequency depends on the desired baud rate
and assumes the worst case scenario can occur in the application.)
Table 18-23 gives examples for the minimum clock frequency in order to ensure proper functionality at
various CAN bus speeds.
Baud Rate
1 Mbit/sec
500 kbit/sec
250 kbit/sec
Table 18-23. Minimum Clock Frequency Requirements
Minimum Clock Frequency
15.25 MHz
7.625 MHz
3.81 MHz
18.11.4 Bit Time Logic Calculation Examples
The calculation of the CAN bus clocks using CKI = 16 MHz is shown in the following examples. The
desired baud rate for both examples is 1 Mbit/s.
Example 1
PSC = PSC[5:0] + 2 = 0 + 2 = 2
TSEG1 = TSEG1[3:0] + 1 = 3 + 1 = 4
TSEG2 = TSEG2[2:0] + 1 = 2 + 1 = 3
SJW = TSEG2 = 3
• Sample point positioned at 62.5% of bit time
• Bit time = 125 ns × (1 + 4 + 3 M 3) = (1 M 0.375) µs
• Bus Clock = 16 MHz / (2 × (1 + 4 + 3)) = 1 Mbit/s (nominal)
166 CAN Module
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