CP3BT23_14 Datasheet, PDF (229/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
23.2 ACB FUNCTIONAL DESCRIPTION
The ACB module provides the physical layer for an ACCESS.bus compliant serial interface. The module is
configurable as either a master or slave device. As a slave, the ACB module may issue a request to
become the bus master.
23.2.1 Master Mode
An ACCESS.bus transaction starts with a master device requesting bus mastership. It sends a Start
Condition, followed by the address of the device it wants to access. If this transaction is successfully
completed, software can assume that the device has become the bus master.
For a device to become the bus master, software should perform the following steps:
1. Set the ACBCTL1.START bit, and configure the ACBCTL1.INTEN bit to the desired operation mode
(Polling or Interrupt). This causes the ACB to issue a Start Condition on the ACCESS.bus, as soon as
the ACCESS.bus is free (ACBCST.BB=0). It then stalls the bus by holding SCL low.
2. If a bus conflict is detected, (i.e., some other device pulls down the SCL signal before this device
does), the ACBST.BER bit is set.
3. If there is no bus conflict, the ACBST.MASTER and ACBST.SDAST bits are set.
4. If the ACBCTL1.INTEN bit is set, and either the ACBST.BER bit or the ACBST.SDAST bit is set, an
interrupt is sent to the ICU.
Sending the Address Byte
Once this device is the active master of the ACCESS.bus (ACBST.MASTER = 1), it can send the address
on the bus. The address should not be this device’s own address as specified in the ACBADDR.ADDR
field if the ACBADDR.SAEN bit is set or the ACBADDR2.ADDR field if the ACBADDR2.SAEN bit is set,
nor should it be the global call address if the ACBST.GCMTCH bit is set.
To send the address byte use the following sequence:
1. Configure the ACBCTL1.INTEN bit according to the desired operation mode. For a receive transaction
where software wants only one byte of data, it should set the ACBCTL1.ACK bit. If only an address
needs to be sent, set the ACBCTL1.STASTRE bit.
2. Write the address byte (7-bit target device address), and the direction bit, to the ACBSDA register. This
causes the module to generate a transaction. At the end of this transaction, the acknowledge bit
received is copied to the ACBST.NEGACK bit. During the transaction, the SDA and SCL signals are
continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted,
the ACBST.BER bit is set, and the ACBST.MASTER bit is cleared.
3. If the ACBCTL1.STASTRE bit is set, and the transaction was successfully completed (i.e., both the
ACBST.BER and ACBST.NEGACK bits are cleared), the ACBST.STASTR bit is set. In this case, the
ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the ACBCTL1.INTE bit is set, it
also sends an interrupt to the core.
4. If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither
the ACBST.NEGACK nor ACBST.BER bit is set, and no other master has accessed the device), the
ACBST.SDAST bit is set to indicate that the module is waiting for service.
5. If the requested direction is receive, the start transaction was completed successfully, and the
ACBCTL1.STASTRE bit is clear, the module starts receiving the first byte automatically.
6. Check that both the ACBST.BER and ACBST.NEGACK bits are clear. If the ACBCTL1.INTEN bit is
set, an interrupt is generated when either the ACBST.BER or ACBST.NEGACK bit is set.
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ACCESS.bus Interface 229