CP3BT23_14 Datasheet, PDF (79/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
12.6.2 Power Management Status Register (PMMSR)
The Management Status Register (PMMR) is a byte-wide, read/write register that provides status signals
for the various clocks. The reset value of PMSR register bits 0 to 2 depend on the status of the clock
sources monitored by the PMM. The upper 5 bits are clear after reset. The format of the register is shown
below.
7
3
2
1
0
Reserved
OHC
OMC
OLC
OLC
OMC
OHC
The Oscillating Low Frequency Clock bit indicates whether the low-frequency oscillator is
producing a stable clock. When the low-frequency oscillator is unavailable, the PMM will not
switch to Power Save, Idle, or Halt mode.
0 – Low-frequency oscillator is unstable, dis-abled, or not oscillating. 1 – Low-frequency
oscillator is available.
The Oscillating Main Clock bit indicates whether the high-frequency oscillator is producing a
stable clock. When the high-frequency IDLE = 1 WBPSM = 1 & IDLE = 1 & "WAIT" Idle
Mode HW Event oscillator is unavailable, the PMM will not switch to Active mode.
0 – High-frequency oscillator is unstable, disabled, or not oscillating.
1 – High-frequency oscillator is available.
The Oscillating High Frequency (PLL) Clock bit indicates whether the PLL is producing a
stable clock. Because the PMM tests the stability of the PLL clock to qualify power mode
state transitions, a stable clock is indicated when the PLL is disabled. This removes the
stability of the PLL clock from the test when the PLL is disabled. When the PLL is enabled
but unstable, the PMM will not switch to Active mode.
0 – PLL is enabled but unstable.
1 – PLL is stable or disabled (CRCTRL.PLL- PWD = 0).
12.7 Switching Between Power Modes
Switching from a higher to a lower power consumption mode is performed by writing an appropriate value
to the Power Management Control/Status Register (PMMCR). Switching from a lower power consumption
mode to the Active mode is usually triggered by a hardware interrupt. Figure 12-1 shows the four power
consumption modes and the events that trigger a transition from one mode to another.
WBPSM = 1 &
HALT = 1 &
"WAIT"
Reset
Active Mode
WBPSM = 0 &PSM = 1
or
WBPSM = 1 & PSM = 1 & "WAIT"
WBPSM = 1 &
IDLE = 1 &
"WAIT"
Power Save Mode _{HW Event}
WBPSM = 1 & IDLE = 1 & "WAIT"
IDLE = 1
Idle Mode
HW Event
Note:
HW Event = MIWU wake-up or NMI
Halt Mode
HW Event
DS008
Figure 12-1. Power Mode State Diagram
Some of the power-up transitions are based on the occurrence of a wake-up event. An event of this type
can be either a maskable interrupt or a non-maskable interrupt (NMI). All of the maskable hardware wake-
up events are monitored by the Multi-Input Wake-Up (MIWU) Module, which is active in all modes. Once a
wake-up event is detected, it is latched until an interrupt acknowledge cycle occurs or a reset is applied.
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