CP3BT23_14 Datasheet, PDF (301/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

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CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Figure 29-15. Microwire Transaction Timing,
Data Echoed to Output, Normal Mode,
SCIDL = 0, ECHO = 1, Slave Mode
29.15 ACCESS.bus Timing
Symbol
tBUFi
tCSTOsi
tCSTRhi
tCSTRsi
tDHCsi
tDLCsi
tSCLfi
tSCLri
tSCLlowi
tSCLhighi
tSDAri
tSDAfl
tSDAhi
tSDAsi
tBUFo
tCSTOso
tCSTRho
tCSTRso
tDHCso
tDLCso
Figure
Figure 29-17
Figure 29-17
Figure 29-17
Figure 29-17
Figure 29-18
Figure 29-17
Figure 29-16
Figure 29-16
Figure 29-19
Figure 29-19
Figure 29-16
Figure 29-16
Figure 29-19
Figure 29-19
Figure 29-17
Figure 29-17
Figure 29-17
Figure 29-18
Figure 29-18
Figure 29-17
Table 29-7. ACCESS.bus Signals
Description
Reference
ACCESS.bus Input Signals
Bus free time between
Stop and Start
Condition
SCL setup time
Before Stop Condition
SCL hold time
After Start Condition
SCL setup time
Before Start Condition
Data High setup time
Before SCL Rising
Edge (RE)
Data Low setup time Before SCL RE
SCL signal rise time
SCL signal fall time
SCL low time
After SCL Falling Edge
(FE)
SCL high time
After SCL RE
SDA signal rise time
SDA signal fall time
SDA hold time
After SCL FE
SDA setup time
Before SCL RE
ACCESS.bus Output Signals
Bus free time between
Stop and Start
Condition
SCL setup time
Before Stop Condition
SCL hold time
After Start Condition
SCL setup time
Before Start Condition
Data High setup time Before SCL R.E.
Data Low setup time Before SCL R.E.
Min (ns)
tSCLhigho
(8 × tCLK) tSCLri
(8 × tCLK) tSCLri
(8 × tCLK) tSCLri
2 × tCLK
2 × tCLK
-
-
16 × tCLK
16 × tCLK
-
-
0
2 × tCLK
tSCLhigho
tSCLhigho
tSCLhigho
tSCLhigho
tSCLhigho -tSDAro
tSCLhigho -tSDAfo
Max (ns)
-
-
-
-
-
-
300
1000
-
-
1000
300
-
-
-
-
-
-
-
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Electrical Characteristics 301