CP3BT23_14 Datasheet, PDF (193/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Within the interrupt handler, the CPU can read out the new CVSD data. If the CPU reads from an already
empty CVSD Out FIFO, a lockup of the FIFO logic may occur which persists until the next reset. Software
must check the CVOUTST field of the CVSTAT register to read the number of valid words in the FIFO.
Software must not use the CVNF bit as an indication of the number of valid words in the FIFO.
20.5 CVSD to PCM CONVERSION
The converter core reads from the CVSD In FIFO every 250 µs and writes a new PCM sample into the
PCMOUT buffer every 125 µs. If the previous PCM data has not yet been transferred to the audio
interface, it will be overwritten with the new PCM sample.
If there are only three unread words left, the CVSD In Nearly Empty bit (CVNE) is set and, if enabled
(CVSDINT = 1), an interrupt request is generated.
If the CVSD In FIFO is empty, the CVSD In Empty bit (CVE) is set and, if enabled (CVSDERRINT = 1), an
interrupt request is generated. If the converter core reads from an already empty CVSD In FIFO, the FIFO
automatically returns a checkerboard pattern to guarantee a minimum level of distortion of the audio
stream.
20.6 INTERRUPT GENERATION
An interrupt is generated in any of the following cases:
• When a new PCM sample has been written into the PCMOUT register and the CVCTRL.PCMINT bit is
set.
• When a new PCM sample has been read from the PCMIN register and the CVCTRL.PCMINT bit is set.
• When the CVSD In FIFO is nearly empty (CVSTAT.CVNE = 1) and the CVCTRL.CVSDINT bit is set.
• When the CVSD Out FIFO is nearly full (CVSTAT.CVNF = 1) and the CVCTRL.CVSDINT bit is set.
• When the CVSD In FIFO is empty (CVSTAT.CVE = 1) and the CVCTRL.CVSDERRINT bit is set.
• When the CVSD Out FIFO is full (CVSTAT.CVF = 1) and the CVCTRL.CVSDERRINT bit is set.
Both the CVSD In and CVSD Out FIFOs have a size of 8 × 16 bit (8 words). The warning limits for the two
FIFOs is set at 5 words. (The CVSD In FIFO interrupt will occur when there are 3 words left in the FIFO,
and the CVSD Out FIFO interrupt will occur when there are 3 or less empty words left in the FIFO.) The
limit is set to 5 words because Bluetooth audio data is transferred in packages composed of 10 or
multiples of 10 bytes.
20.7 DMA SUPPORT
The CVSD module can operate with any of four DMA channels. Four DMA channels are required for
processor independent operation. Both receive and transmit for CVSD data and PCM data can be enabled
individually. The CVSD/ PCM module asserts a DMA request to the on-chip DMA controller under the
following conditions:
• The DMAPO bit is set and the PCMOUT register is full, because it has been updated by the converter
core with a new PCM sample. (The DMA controller can read out one PCM data word from the
PCMOUT register).
• The DMAPI bit is set and the PCMIN register is empty, because it has been read by the converter core
(the DMA controller can write one new PCM data word into the PCMIN register).
• The DMACO bit is set and a new 16-bit CVSD data stream has been copied into the CVSD Out FIFO
(The DMA controller can read out one 16-bit CVSD data word from the CVSD Out FIFO).
• The DMACI bit is set and a 16-bit CVSD data stream has been read from the CVSD In FIFO (The
DMA controller can write one new 16-bit CVSD data word into the CVSD In FIFO).
The CVSD/PCM module only supports indirect DMA transfers. Therefore, transferring PCM data between
the CVSD/ PCM module and another on-chip module requires two bus cycles.
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CVSD/PCM Conversion Module 193