CP3BT23_14 Datasheet, PDF (219/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
In slave mode, an optional fourth signal (MWCS) may be used to enable the slave transmit. At any given
time, only one slave can respond to the master. Each slave device has its own chip select signal (MWCS)
for this purpose.
Figure 22-2 shows a block diagram of the enhanced Microwire serial interface in the device.
22.1.1 Shifting
The Microwire interface is a full duplex transmitter/receiver. A 16-bit shifter, which can be split into a low
and high byte, is used for both transmitting and receiving. In 8-bit mode, only the lower 8-bits are used to
transfer data. The transmitted data is shifted out through MDODI pin (master mode) or MDIDO pin (slave
mode), starting with the most significant bit. At the same time, the received data is shifted in through
MDIDO pin (master mode) or MDODI pin (slave mode), also starting with the most significant bit first.
The shift in and shift out are controlled by the MSK clock. In each clock cycle of MSK, one bit of data is
transmitted/received. The 16-bit shifter is accessible as the MWDAT register. Reading the MWDAT
register returns the value in the read buffer. Writing to the MWDAT register updates the 16bit shifter.
Interrupt
Request
Control + Status
MWCS
Write
Data
Write
Data
16-BIt Read Buffer
8 8 MWnDAT
16-BIt Shift Register
Data Out
Slave
Master
MDODI
Data In
Slave
Master
MDIDO
MSK
MSK
PCLK
Clock
Clock Prescaler + Select
Master
DS469
Figure 22-2. Microwire Block Diagram
22.1.2 Reading
The enhanced Microwire interface implements a double buffer on read. As illustrated in Figure 22-2, the
double read buffer consists of the 16-bit shifter and a buffer, called the read buffer.
The 16-bit shifter loads the read buffer with new data when the data transfer sequence is completed and
previous data in the read buffer has been read. In master mode, an Overrun error occurs when the read
buffer is full, the 16-bit shifter is full and a new data transfer sequence starts.
When 8-bit mode is selected, the lower byte of the shift register is loaded into the lower byte of the read
buffer and the read buffer’s higher byte remains unchanged.
The RBF bit indicates if the MWDAT register holds valid data. The OVR bit indicates that an overrun
condition has occurred.
22.1.3 Writing
The BSY bit indicates whether the MWDAT register can be written. All write operations to the MWDAT
register update the shifter while the data contained in the read buffer is not affected. Undefined results will
occur if the MWDAT register is written to while the BSY bit is set.
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Microwire/SPI Interface 219