CP3BT23_14 Datasheet, PDF (76/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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The Random Number Generator (RNG) module has two oscillators which operate independently of the
rest of the system. For maximum power savings, software must disable these oscillators.
12.1 ACTIVE MODE
In Active mode, the high-frequency oscillator is active and generates the 12-MHz Main Clock. The 32.768
kHz oscillator is active and may be used to generate the Slow Clock. The PLL can be active or inactive,
as required. Most on-chip modules are driven by the System Clock. The System Clock can be the PLL
Clock after a programmable divider or the 12-MHz Main Clock. The activity of peripheral modules is
controlled by their enable bits.
Power consumption can be reduced in this mode by selectively disabling modules and by executing the
WAIT instruction. When the WAIT instruction is executed, the CPU stops executing new instructions until it
receives an interrupt signal. After reset, the CP3BT23 is in Active Mode.
12.2 POWER SAVE MODE
In Power Save mode, Slow Clock is used as the System Clock which drives the CPU and most on-chip
modules. If Slow Clock is driven by the 32.768 kHz oscillator and no onchip module currently requires the
12-MHz Main Clock, software can disable the high-frequency oscillator to further reduce power
consumption. Auxiliary Clocks 1 and 2 can be turned off under software control before switching to a
reduced power mode, or they may remain active as long as Main Clock is also active. If the system does
not require the PLL output clock, the PLL can be disabled. Alternatively, the Main Clock and the PLL can
also be controlled by the Hardware Clock Control function, if enabled. The clock architecture is described
in Section 11.0.
The Bluetooth LLC can either be switched to the 32 kHz clock internally in the module, or it remains
running off Auxiliary clock 1 as long as the Main Clock and Auxiliary Clock 1 are enabled.
In Power Save mode, some modules are disabled or their operation is restricted. Other modules, including
the CPU, continue to function normally, but operate at a reduced clock rate. Details of each module’s
activity in Power Save mode are described in each module’s descriptions.
It is recommended to keep CPU activity at a minimum by executing the WAIT instruction to guarantee low
power consumption in the system.
12.3 IDLE MODE
In Idle mode, the System Clock is disabled and therefore the clock is stopped to most modules of the
device. The PLL and the high-frequency oscillator may be disabled as controlled by register bits. The low-
frequency oscillator remains active. The Power Management Module (PMM) and the Timing and
Watchdog Module (TWM) continue to operate off the Slow Clock. Auxiliary Clocks 1 and 2 can be turned
off under software control before switching to a power saving mode, or they remain active as long as Main
Clock is also active. Alternatively, the 12 MHz Main Clock and the PLL can also be controlled by the
Hardware Clock Control function, if enabled.
The Bluetooth LLC can either be switched to the Slow Clock internally in the module or it remains running
off the Auxiliary Clock 1 as long as the Main Clock and Auxiliary Clock 1 are enabled.
12.4 HALT MODE
In Halt mode, all the device clocks, including the System Clock, Main Clock, and Slow Clock, are disabled.
The highfrequency oscillator and PLL are turned off. The low-frequency oscillator continues to operate,
however its circuitry is optimized to guarantee lowest possible power consumption. This mode allows the
device to reach the absolute minimum power consumption without losing its state (memory, registers,
etc.).
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Power Management
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