CP3BT23_14 Datasheet, PDF (149/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
18.10 CAN Controller Registers
Name
CNSTAT
CGCR0
CTIM0
GMSKX0
GMSKB0
BMSKX0
BMSKB0
CIEN0
CIPND0
CICLR0
CICEN0
CSTPND0
CANEC0
CEDIAG0
CTMR0
CGCR1
CTIM1
GMSKX1
GMSKB1
BMSKX1
BMSKB1
CIEN1
CIPND1
CICLR1
CICEN1
CSTPND1
CANEC1
CEDIAG1
CTMR1
Table 18-8. CAN Controller Registers
Address
See Table 18-7
0E F100h
0E F102h
0E F104h
0E F106h
0E F108h
0E F10Ah
0E F10Ch
0E F10Eh
0E F110h
0E F112h
0E F114h
0E F116h
0E F118h
0E F11Ah
0E F300h
0E F302h
0E F304h
0E F306h
0E F308h
0E F30Ah
0E F30Ch
0E F30Eh
0E F310h
0E F312h
0E F314h
0E F316h
0E F318h
0E F31Ah
Description
CAN Buffer Status/ Control Register
AN Global Configuration Register 0
CAN Timing Register 0
Global Mask Register 0
Global Mask Register 0
Basic Mask Register 0
Basic Mask Register 0
CAN Interrupt Enable Register 0
CAN Interrupt Pending Register 0
CAN Interrupt Clear Register 0
CAN Interrupt Code Enable Register 0
CAN Status Pending Register 0
CAN Error Counter Register 0
CAN Error Diagnostic Register 0
CAN Timer Register 0
CAN Global Configuration Register 1
CAN Timing Register 1
Global Mask Register 1
Global Mask Register 1
Basic Mask Register 1
Basic Mask Register 1
CAN Interrupt Enable Register 1
CAN Interrupt Pending Register 1
CAN Interrupt Clear Register 1
CAN Interrupt Code Enable Register 1
CAN Status Pending Register 1
CAN Error Counter Register 1
CAN Error Diagnostic Register 1
CAN Timer Register 1
18.10.1 Buffer Status/Control Register (CNSTAT)
The buffer status (ST), the buffer priority (PRI), and the data length code (DLC) are controlled by
manipulating the contents of the Buffer Status/Control Register (CNSTAT). The CPU and CAN module
have access to this register.
15
12
11
8
7
4
3
0
DLC
Reserved
PRI
ST
0
R/W
ST The Buffer Status field contains the status information of the buffer as shown in Table 18-9. This
field can be modified by the CAN module. The ST0 bits acts as a buffer busy indication. When
the BUSY bit is set, any write access to the buffer is disabled with the exception of the lower byte
of the CNSTAT register. The CAN module sets this bit if the buffer data is currently copied from
the hidden buffer or if a message is scheduled for transmission or is currently transmitting. The
CAN module always clears this bit on a status update.
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