CP3BT23_14 Datasheet, PDF (263/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
26.1.3 Dual 16-Bit Capture Mode
In addition to the two PWM modes, each timer subsystem may be configured to operate in an input
capture mode which provides two 16-bit capture channels. The input capture mode can be used to
precisely measure the period and duty cycle of external signals.
In capture mode the counter COUNTx operates as a 16-bit up-counter while the two TIOx pins associated
with a timer subsystem operate as capture inputs. A capture event on the TIOx pins causes the contents
of the counter register (COUNTx) to be copied to the PERCAPx or DTYCAPx registers respectively.
Starting the counter is identical to the 16-bit PWM mode, i.e. setting the lower of the two MODE.TxRUN
bits will start the counter and the clock prescaler. In addition, the capture event inputs are enabled once
the MODE.TxRUN bit is set.
The TIOx capture inputs can be independently configured to detect a capture event on either a positive
transition, a negative transition or both a positive and a negative transition. In addition, any capture event
may be used to reset the counter COUNTx and the clock prescaler counter. This avoids the need for
software to keep track of timer overflow conditions and greatly simplifies the direct frequency and duty
cycle measurement of an external signal.
Figure 26-5 illustrates the configuration of a timer subsystem while operating in capture mode. The
numbering in Figure 26-5 refers to timer subsystem 1 but equally applies to the other three timer
subsystems.
7
0
C1PRSC
==
Prescaler
Counter
T MO D1= 11
15
Restart
T1RUN
COUNT1_n[15:0]
Compare
PERCAP1_n[15:0]
Compare
DTYCAP1_n[15:0]
0
15:0
cap
cap
rst
rst
2
0
C1EDG
TIOn_1
2
0
C2EDG
TIOn_2
DS357
Figure 26-5. VTU Dual 16-bit Capture Mode
26.1.4 Low Power Mode
In case a timer subsystem is not used, software can place it in a low-power mode. All clocks to a timer
subsystem are stopped and the counter and prescaler contents are frozen once low-power mode is
entered. Software may continue to write to the MODE, INTCTL, IOxCTL, and CLKxPS registers. Write
operations to the INTPND register are allowed; but if a timer subsystem is in low-power mode, its
associated interrupt pending bits cannot be cleared. Software cannot write to the COUNTx, PERCAPx,
and DTYCAPx registers of a timer subsystem while it is in low-power mode. All registers can be read at
any time.
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Versatile Timer Unit (VTU) 263