CP3BT23_14 Datasheet, PDF (4/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
www.ti.com
3 Device Overview
The CP3BT23 connectivity processor is a complete microcomputer with all system timing, interrupt logic,
program memory, data memory, and I/O ports included on-chip, making it well-suited to a wide range of
embedded applications. Figure 1-1 shows the major on-chip components of the CP3BT23 devices.
3.1 CR16C CPU CORE
The CP3BT23 device implements the CR16C CPU core module. The high performance of the CPU core
results from the implementation of a pipelined architecture with a twobytes-per-cycle pipelined system bus.
As a result, the CPU can support a peak execution rate of one instruction per clock cycle.
For more information, please refer to the CR16C Programmer’s Reference Manual (document number
424521772-101).
3.2 MEMORY
The CP3BT23 devices support a uniform linear address space of up to 16 megabytes. Three types of on-
chip memory occupy specific regions within this address space, along with any external memory:
• 256K bytes of Flash program memory
• 8K bytes of Flash data memory
• 32K bytes of static RAM
• Up to 12M bytes of external memory (144-pin devices)
The 256K bytes of Flash program memory are used to store the application program, Bluetooth protocol
stack, and realtime operating system. The Flash memory has security features to prevent unintentional
programming and to prevent unauthorized access to the program code. This memory can be programmed
with an external programming unit or with the device installed in the application system (in-system
programming).
The 8K bytes of Flash data memory are used for non-volatile storage of data entered by the end-user,
such as configuration settings.
The 32K bytes of static RAM are used for temporary storage of data and for the program stack and
interrupt stack. Read and write operations can be byte-wide or word-wide, depending on the instruction
executed by the CPU.
Up to 12M bytes of external memory can be added on an external bus. The external bus is only available
on devices in 144-pin packages.
For Flash program and data memory, the device internally generates the necessary voltages for
programming. No additional power supply is required.
3.3 INPUT/OUTPUT PORTS
The device has up to 50 software-configurable I/O pins, organized into seven ports called Port B, Port C,
Port E, Port G, Port H, Port I, and Port J. Each pin can be configured to operate as a general-purpose
input or general-purpose output. In addition, many I/O pins can be configured to operate as inputs or
outputs for on-chip peripheral modules such as the UART, timers, or Microwire/SPI interface.
The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-
STATE output, pushpull output, weak pull-up input, or high-impedance input.
4
Device Overview
Submit Documentation Feedback
Product Folder Links: CP3BT23
Copyright © 2013–2014, Texas Instruments Incorporated