CP3BT23_14 Datasheet, PDF (38/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Name
Protection Word
Other (User Data)
Table 8-4. Information Block 1
Address Range
0FEh–0FFh
080h–0FDh
Read Access
Yes
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Write Access
Write access only if section
write enable bit is set and
global write protection is
disabled.
8.2.4 Main Block 2
Main Block 2 holds the 8K-byte data area, which consists of sixteen 512-byte sections. Write access by
the CPU to Main Block 2 is controlled by the corresponding bits in the FSM0WER register. The least
significant bit in the register controls the section at the lowest address.
8.2.5 Information Block 2
Information Block 2 contains 128 bytes, which can be used to store user data. The CPU can always read
Information Block 2. The CPU can write Information Block 2 only when global write protection is disabled.
Erasing Information Block 2 also erases Main Block 2.
8.3 FLASH MEMORY OPERATIONS
Flash memory programming (erasing and writing) can be performed on the flash data memory while the
CPU is executing out of flash program memory. Although the CPU can execute out of flash data memory,
it cannot erase or write the flash program memory while executing from flash data memory. To erase or
write the flash program memory, the CPU must be executing from the on-chip static RAM or offchip
memory.
An erase operation is required before programming. An erase operation sets all of the bits in the erased
region. A programming operation clears selected bits.
The programming mechanism is pipelined, so that a new write request can be loaded while a previous
request is in progress. When the FMFULL bit in the FMSTAT or FSMSTAT register is clear, the pipeline is
ready to receive a new request. New requests may be loaded after checking only the FMFULL bit.
8.3.1 Main Block Read
Read accesses from flash program memory can only occur when the flash program memory is not busy
from a previous write or erase operation. Read accesses from the flash data memory can only occur when
both the flash program memory and the flash data memory are not busy. Both byte and word read
operations are supported.
8.3.2 Information Block Read
Information block data is read through the register-based interface. Only word read operations are
supported and the read address must be word-aligned (LSB = 0). The following steps are used to read
from an information block:
1. Load the word address in the Flash Memory Information Block Address (FMIBAR) or Flash Slave
Memory Information Block Address (FSMIBAR) register.
2. Read the data word by reading out the Flash Memory Information Block Data (FMIBDR) or Flash Slave
Memory Information Block Data (FSMIBDR) register.
8.3.3 Main Block Page Erase
A flash erase operation sets all of the bits in the erased region. Pages of a main block can be individually
erased if their write enable bits are set. This method cannot be used to erase the boot area, if defined.
Each page in Main Block 0 and 1 consists of 1024 bytes (512 words). Each page in Main Block 2 consists
of 512 bytes (256 words). To erase a page, the following steps are performed:
1. Verify that the Flash Memory Busy (FMBUSY) bit in the FMSTAT or FSMSTAT register is clear.
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Flash Memory
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