CP3BT23_14 Datasheet, PDF (114/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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16.3 ADC Operation in Power-Saving Modes
To reduce the level of switching noise in the environment of the ADC, it is possible to operate the
CP3BT23 in low-power modes, in which the System Clock is slowed or switched off. Under these
conditions, Auxiliary Clock 2 can be selected as the clock source for the ADC module, however
conversion results cannot be read by the system while the System Clock is suspended. The expected
operation in power-saving modes is therefore:
1. ADC is configured and a conversion is primed or triggered.
2. A power-saving mode is entered.
3. ADC conversion completes and a wake-up signal is asserted to the MIWU unit.
4. Device wakes up and processes the conversion result.
To conserve power, the ADC should be disabled before entering a low-power mode if its function is not
required.
16.4 Freeze
The ADC module provides support for an In-System Emulator by means of a special FREEZE input. When
FREEZE is asserted the module will exhibit the following specific behavior:
• The automatic clear-on-read function of the result register (ADCRESLT) is disabled.
• The FIFO is updated as usual, and an interrupt for a completed conversion can be asserted.
16.5 ADC Register Set
Name
ADCGCR
ADCACR
ADCCNTRL
ADCSTART
ADCSCDLY
ADCRESLT
Table 16-1. ADC Registers
Address
FF F3C0h
FF F3C2h
FF F3C4h
FF F3C6h
FF F3C8h
FF F3CAh
Description
ADC Global Configuration Register
ADC Auxiliary Configuration Register
ADC Conversion Control Register
ADC Start Conversion Register
ADC Start Conversion Delay Register
ADC Result Register
16.5.1 ADC Global Configuration Register (ADCGCR)
The ADCGCR register controls the basic operation of the interface. The CPU bus master has read/write
access to the ADCGCR register. After reset this register is set to 0000h
8
7
6
5
TOUCH_CFG
4
3
MUX_CFG
2
DIFF
1
0
ADCIN CLKE
N
15
MUXOUTEN
14
INTEN
13
12
Res.
NREF_CFG
11
10
9
PREF_CFG
CLKEN
The Clock Enable bit controls whether the ADC module is running. When this bit is clear, all
ADC clocks are disabled, the ADC analog circuits are in a low-power state, and ADC
registers (other than the ADCGCR and AGCACR registers) are not writeable. Clearing this
bit reinitializes the ADC state machine and cancels any pending trigger event. When this bit
is set, the ADC clocks are enabled and the ADC analog circuits are powered up. The
converter is operational within 0.25 µs of being enabled.
0 – ADC disabled.
1 – ADC enabled.
114 12-Bit Analog to Digital Converter
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