CP3BT23_14 Datasheet, PDF (46/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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FMBUSY
FMFULL
DERR
The Flash Memory Busy bit indicates whether the flash memory (either main block or
information block) is busy being programmed or erased. During that time, software must not
request any further flash memory operations. If such an attempt is made, the CPU is
stopped as long as the FMBUSY bit is active. The CPU must not attempt to read from
program memory (including instruction fetches) while it is busy.
0 – Flash memory is ready to receive a new erase or programming request.
1 – Flash memory busy with previous erase or programming operation.
The Flash Memory Buffer Full bit indicates whether the write buffer for programming is full
or not. When the buffer is full, new erase and write requests may not be made. The
IENPROG bit can be enabled to trigger an interrupt when the buffer is ready to receive a
new request.
0 – Buffer is ready to receive new erase or write requests.
1 – Buffer is full. No new erase or write requests can be accepted.
The Data Loss Error bit indicates that a buffer overrun has occurred during a programming
sequence. After a data loss error occurs, software can clear the DERR bit by writing a 1 to
it. Writing a 0 to the DERR bit has no effect. Software must not change this bit while the
flash program memory is busy being programmed or erased.
0 – No data loss error occurred.
1 – Data loss error occurred.
8.5.8 Flash Memory Prescaler Register (FMPSR/ FSMPSR)
The FMPSR register is a byte-wide read/write register that selects the prescaler divider ratio. The CPU
must not modify this register while an erase or programming operation is in progress (FMBUSY is set). At
reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write
access to this register.
7
5
4
0
Reserved
FTDIV
FTDIV
The prescaler divisor scales the frequency of the System Clock by a factor of (FTDIV + 1).
8.5.9 Flash Memory Start Time Reload Register (FMSTART/FSMSTART)
The FMSTART/FSMSTART register is a byte-wide read/ write register that controls the program/erase
start delay time. Software must not modify this register while a program/erase operation is in progress
(FMBUSY set). At reset, this register is initialized to 18h if the flash memory is idle. The CPU bus master
has read/write access to this register.
7
0
FTSTART
FTSTART The Flash Timing Start Delay Count field generates a delay of (FTSTART + 1) prescaler
output clocks.
46
Flash Memory
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