CP3BT23_14 Datasheet, PDF (237/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
23.3.7 ACB Own Address Register 1 (ACBADDR1)
The ACBADDR1 register is a byte-wide, read/write register that holds the module’s first ACCESS.bus
address. After reset, its value is undefined.
7
6
0
SAEN
ADDR
ADDR
SAEN
The Own Address field holds the first 7-bit ACCESS.bus address of this device. When in
slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit
received to bit 6, and the last to bit 0). If the address field matches the received data and the
SAEN bit is set, a match is detected.
The Slave Address Enable bit controls whether address matching is performed in slave
mode. When set, the SAEN bit indicates that the ADDR field holds a valid address and
enables the match of ADDR to an incoming address byte. When cleared, the ACB does not
check for an address match.
0 – Address matching disabled.
1 – Address matching enabled0.
23.3.8 ACB Own Address Register 2 (ACBADDR2)
The ACBADDR2 register is a byte-wide, read/write register that holds the module’s second ACCESS.bus
address. After reset, its value is undefined.
7
6
0
SAEN
ADDR
ADDR
SAEN
The Own Address field holds the second 7-bit ACCESS.bus address of this device. When in
slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit
received to bit 6, and the last to bit 0). If the address field matches the received data and the
SAEN bit is set, a match is detected.
The Slave Address Enable bit controls whether address matching is performed in slave
mode. When set, the SAEN bit indicates that the ADDR field holds a valid address and
enables the match of ADDR to an incoming address byte. When cleared, the ACB does not
check for an address match.
0 – Address matching disabled.
1 – Address matching enabled.
23.4 USAGE HINTS
• When the ACB module is disabled, the ACBCST.BB bit is cleared. After enabling the ACB
(ACBCTL2.ENABLE
=
1) in systems with more than one master, the bus may be in the middle of a transaction with another
device, which is not reflected in the BB bit. There is a need to allow the ACB to synchronize to the bus
activity status before issuing a request to become the bus master, to prevent bus errors. Therefore,
before issuing a request to become the bus master for the first time, software should check that there
is no activity on the bus by checking the BB bit after the bus allowed time-out period.
• When waking up from power down, before checking the ACBCST.MATCH bit, test the ACBCST.BUSY
bit to make sure that the address transaction has finished.
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ACCESS.bus Interface 237