CP3BT23_14 Datasheet, PDF (191/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
20 CVSD/PCM Conversion Module
The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD
encoding is as defined in the Bluetooth specification and the PCM encoding may be 8-bit µ-Law, 8-bit A-
Law, or 13-bit to 16-bit Linear.
The CVSD conversion module operates at a fixed rate of 125 µs (8 kHz) per PCM sample. On the CVSD
side, there is a read and a write FIFO allowing up to 8 words of data to be read or written at the same
time. On the PCM side, there is a double-buffered register requiring data to be read and written every 125
µs. The intended use is to move CVSD data into the module with a CVSD interrupt handler, and to move
PCM data with DMA. Figure 20-1 shows a block diagram of the CVSD to PCM module.
2 MHz
Clock Input
Interrupt
DMA
16-Bit 8 kHz
u/A-Law
16-Bit 8 kHz
u/A-Law
16-Bit
CVSD
64 kHz ^Encoder
Filter
Engine
16-Bit
CVSD
64 kHz ^Decoder
1-Bit 64 kHz
16-Bit Shift Reg
1-Bit 64 kHz
16-Bit Shift Reg
Peripheral Bus
DS058
Figure 20-1. CVSD/PCM Converter Block Diagram
20.1 OPERATION
The Aux2 clock (generated by the Clock module described in Section 11.9) must be configured, because it
drives the CVSD module. Software must set its prescaler to provide a 2 MHz input clock based upon the
System Clock (usually 12 MHz). This is done by writing an appropriate divisor to the ACDIV2 field of the
PRSAC register. Software must also enable the Aux2 clock by setting the ACE2 bit within the CRCTRL
register. For example:
PRSAC &= 0x0f;
// Set Aux2 prescaler to generate
// 2 MHz (Fsys = 12 MHz)
PRSAC |= 0x50;
CRCTRL |= ACE2; // Enable Aux2 clk
The module converts between PCM data and CVSD data at a fixed rate of 8 kHz per PCM sample. Due to
compression, the data rate on the CVSD side is only 4 kHz per CVSD sample.
If PCM interrupts are enabled (PCMINT is set) every 125 µs (8 kHz) an interrupt will occur and the
interrupt handler can operate on some or all of the four audio streams CVSD in, CVSD out, PCM in, and
PCM out. Alternatively, a DMA request is issued every 125 µs and the DMA controller is used to move the
PCM data between the CVSD/PCM module and the audio interface.
If CVSD interrupts are enabled, an interrupt is issued when either one of the CVSD FIFOs is almost empty
or almost full. On the PCM data side there is double buffering, and on the CVSD side there is an eight
word (8 × 16-bit) FIFO for the read and write paths.
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CVSD/PCM Conversion Module 191