CP3BT23_14 Datasheet, PDF (209/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
UPSC
The Prescaler field specifies the prescaler value used for dividing the System Clock in the
first stage of the two-stage divider chain. For the prescaler factors corresponding to each 5bit
value, see Figure 21-1.
UDIV10:8 The Baud Rate Divisor field holds the three most significant bits (bits 10, 9, and 8) of the
UART baud rate divisor used in the second stage of the two-stage divider chain. The
remaining bits of the baud rate divisor are held in the UnBAUD register.
21.3.4 UART Baud Rate Divisor (UnBAUD)
The UnBAUD register is a byte-wide, read/write register that contains the lower eight bits of the baud rate
divisor. The register contents are unknown at power-up and are left unchanged by a reset operation. The
register format is shown below.
7
0
UDIV7:0
UDIV7:0
The The Baud Rate Divisor field holds the eight lowest-order bits of the UART baud rate
divisor used in the second stage of the two-stage divider chain. The three most significant
bits are held in the UnPSR register. The divisor value used is (UDIV[10:0] + 1).
21.3.5 UART Frame Select Register (UnFRS)
The UnFRS register is a byte-wide, read/write register that controls the frame format, including the number
of data bits, number of stop bits, and parity type. This register is cleared upon reset. The register format is
shown below.
7
Reserved
6
UPEN
5
4
UPSEL
3
UXB9
2
USTP
1
0
UCHAR
UCHAR
USTP
UXB9
UPSEL
UPEN
The Character Frame Format field selects the number of data bits per frame, not including
the parity bit, as follows:
00 – 8 data bits per frame.
01 – 7 data bits per frame.
10 – 9 data bits per frame.
11 – Loop-back mode, 9 data bits per frame.
The Stop Bits bit specifies the number of stop bits transmitted in each frame. If this bit is 0,
one stop bit is transmitted. If this bit is 1, two stop bits are transmitted.
0 – One stop bit per frame.
1 – Two stop bits per frame.
The Transmit 9th Data Bit holds the value of the ninth data bit, either 0 or 1, transmitted
when the UART is configured to transmit nine data bits per frame. It has no effect when the
UART is configured to transmit seven or eight data bits per frame.
The Parity Select field selects the treatment of the parity bit. When the UART is configured
to transmit nine data bits per frame, the parity bit is omitted and the UPSEL field is ignored.
00 – Odd parity.
01 – Even parity.
10 – No parity, transmit 1 (mark).
11 – No parity, transmit 0 (space).
The Parity Enable bit enables or disables parity generation and parity checking. When the
UART is configured to transmit nine data bits per frame, there is no parity bit and the
UnPEN bit is ignored.
0 – Parity generation and checking disabled.
1 – Parity generation and checking enabled.
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