CP3BT23_14 Datasheet, PDF (52/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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9.2.2 Indirect (Memory-To-Memory) Transfers
In indirect (memory-to-memory) mode, data transfers use two consecutive bus cycles. The data is first
read into a temporary register, and then written to the destination in the following cycle. This mode is
slower than the direct (flyby) mode, but it provides support for different source and destination bus widths.
Indirect mode must be used for transfers between memory devices.
If an intermittent bus policy is used, the maximum throughput is one transfer for every five clock cycles. If
a continuous bus policy is used, maximum throughput is one transfer for every two clock cycles.
When the DMACNTLn.DIR bit is 0, the first bus cycle reads data from the source using the ADCAn
counter, while the second bus cycle writes the data into the destination using the ADCBn counter. When
the DMACNTLn.DIR bit is set, the first bus cycle reads data from the source using the ADCBn counter,
while the second bus cycle writes the data into the destination addressed by the ADCAn counter.
The number of bytes transferred in each cycle is taken from the DMACNTLn.TCS register bit. After the
data item has been transferred, the BLTCn counter is decremented by one. The ADCAn and ADCBn
counters are updated according to the INCA, INCB, ADA, and ADB fields in the DMACNTLn register.
9.3 OPERATION MODES
The DMAC operates in three different block transfer modes: Single transfer, double buffer, and auto-
initialize.
9.3.1 Single Transfer Operation
This mode provides the simplest way to accomplish a single block data transfer.
Initialization
1. Write the block transfer addresses and byte count into the corresponding ADCAn, ADCBn, and BLTCn
counters.
2. Clear the DMACNTLn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing
a 1 to it.
3. Set the DMACNTLn.CHEN bit to activate the channel and enable it to respond to DMA transfer
requests.
Termination
When the BLTCn counter reaches 0:
1. The transfer operation terminates.
2. The DMASTAT.TC and DMASTAT.OVR bits are set, and the DMASTAT.CHAC bit is cleared.
3. An interrupt is generated if enabled by the DMACNTLn.ETC or DMACNTLn.EOVR bits.
The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely
starting a new DMA transfer.
52
DMA Controller
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