CP3BT23_14 Datasheet, PDF (57/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
ETC If the Enable Interrupt on Terminal Count bit is set, it enables an interrupt when the
DMASTAT.TC bit is set.
0 – Interrupt disabled.
1 – Interrupt enabled.
EOVR
If the Enable Interrupt on OVR bit is set, it enables an interrupt when the DMASTAT.OVR bit is
set.
0 – Interrupt disabled.
1 – Interrupt enabled.
TCS The Transfer Cycle Size bit specifies the number of bytes transferred in each DMA transfer
cycle. In direct (fly-by) mode, undefined results occur if the TCS bit is not equal to the addressed
memory bus width.
0 – Byte transfers (8 bits per cycle).
1 – Word transfers (16 bits per cycle).
IND The Direct/Indirect Transfer bit specifies the transfer type.
0 – Direct transfer (flyby).
1 – Indirect transfer (memory-to-memory).
DIR The Transfer Direction bit specifies the direction of the transfer relative to Device A.
0 – Device A (pointed to by the ADCAn register) is the source. In Fly-By mode a read
transaction is initialized.
1 – Device A (pointed to by the ADCAn register) is the destination. In Fly-By mode a write
transaction is initialized.
OT The Operation Type bit specifies the operation mode of the DMA controller. enabled.
0 – Single-buffer mode or double-buffer mode enabled.
1 – Auto-Initialize mode
BPC
The Bus Policy Control bit specifies the bus policy applied by the DMA controller. The operation
mode can be either intermittent (cycle stealing) or continuous (burst).
0 – Intermittent operation. The DMAC channel relinquishes the bus after each transaction, even
if the request is still asserted.
1 – Continuous operation. The DMAC channel n uses the bus continuously as long as the
request is asserted. This mode can only be used for software DMA requests. For hardware DMA
requests, the BPC bit must be clear.
SWRQ The Software DMA Request bit is written with a 1 to initiate a software DMA request. Writing a 0
to this bit deactivates the software DMA request. The SWRQ bit must only be written when the
DMRQ signal for this channel is inactive (DMASTAT.CHAC = 0).
0 – Software DMA request is inactive.
1 – Software DMA request is active.
ADA
If the Device A Address Control bit is set, it enables updating the Device A address.
0 – ADCAn address unchanged.
1 – ADCAn address incremented or decremented, according to INCA field of DMACNTLn
register.
INCA
The Increment/Decrement ADCAn field specifies the step size for the Device A address
increment/decrement.
00 – Increment ADCAn register by 1.
01 – Increment ADCAn register by 2.
10 – Decrement ADCAn register by 1.
11 – Decrement ADCAn register by 2.
ADB
If the Device B Address Control bit is set, it enables updating the Device B Address.
0 – ADCBn address unchanged.
1 – ADCBn address incremented or decremented, according to INCB field of DMACNTLn
register.
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