CP3BT23_14 Datasheet, PDF (200/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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21.2 UART OPERATION
The UART has two basic modes of operation: synchronous and asynchronous. Synchronous mode is only
supported for the UART0 module. In addition, there are two specialpurpose modes, called attention and
diagnostic. This section describes the operating modes of the UART.
21.2.1 Asynchronous Mode
The asynchronous mode of the UART enables the device to communicate with other devices using just
two communication signals: transmit and receive.
In asynchronous mode, the transmit shift register (TSFT) and the transmit buffer (UnTBUF) double-buffer
the data for transmission. To transmit a character, a data byte is loaded in the UnTBUF register. The data
is then transferred to the TSFT register. While the TSFT register is shifting out the current character (LSB
first) on the TXD pin, the UnTBUF register is loaded by software with the next byte to be transmitted.
When TSFT finishes transmission of the last stop bit of the current frame, the contents of UnTBUF are
transferred to the TSFT register and the Transmit Buffer Empty bit (UTBE) is set. The UTBE bit is
automatically cleared by the UART when software loads a new character into the UnTBUF register. During
transmission, the UXMIP bit is set high by the UART. This bit is reset only after the UART has sent the
last stop bit of the current character and the UnTBUF register is empty. The UnTBUF register is a
read/write register. The TSFT register is not software accessible.
In asynchronous mode, the input frequency to the UART is 16 times the baud rate. In other words, there
are 16 clock cycles per bit time. In asynchronous mode, the baud rate generator is always the UART clock
source.
The receive shift register (RSFT) and the receive buffer (UnRBUF) double buffer the data being received.
The UART receiver continuously monitors the signal on the RXD pin for a low level to detect the beginning
of a start bit. On sensing this low level, the UART waits for seven input clock cycles and samples again
three times. If all three samples still indicate a valid low, then the receiver considers this to be a valid start
bit, and the remaining bits in the character frame are each sampled three times, around the mid-bit
position. For any bit following the start bit, the logic value is found by majority voting, i.e. the two samples
with the same value define the value of the data bit. Figure 21-2 illustrates the process of start bit
detection and bit sampling.
Data bits are sensed by taking a majority vote of three samples latched near the midpoint of each baud
(bit time). Normally, the position of the samples within the baud is determined automatically, but software
can override the automatic selection by setting the USMD bit in the UnMDSL2 register and programming
the UnSPOS register.
Serial data input on the RXD pin is shifted into the RSFT register. On receiving the complete character,
the contents of the RSFT register are copied into the UnRBUF register and the Receive Buffer Full bit
(URBF) is set. The URBF bit is automatically cleared when software reads the character from the URBUF
register. The RSFT register is not software accessible.
200 UART Modules
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