CP3BT23_14 Datasheet, PDF (161/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
18.10.13 CAN Interrupt Code Enable Register (CICENn)
The CICENn register controls whether the interrupt pending flag in the CIPNDn register is translated into
the Interrupt Code field of the CSTPNDn register. All interrupt requests, CAN error, and message buffer
interrupts can be enabled/ disabled separately for the interrupt code indication field.
15
14
0
EICEN
ICEN
0
R/W
EICEN
ICEN
The Error Interrupt Code Enable bit controls encoding for error interrupts.
0 – Error interrupt pending is not indicated in the interrupt code.
1 – Error interrupt pending is indicated in the interrupt code.
The Buffer Interrupt Code Enable bits control encoding for message buffer interrupts.
0 – Message buffer interrupt pending is not indicated in the interrupt code.
1 – Message buffer interrupt pending is indicated in the interrupt code.
18.10.14 CAN Status Pending Register (CSTPNDn)
The CSTPNDn register holds the status of the CAN Node and the Interrupt Code.
15
Reserved
8
7
5
4
3
0
NS
IRQ
IST
0
R
NS The CAN Node Status field indicates the status of the CAN node as shown in Table 18-18T.
Table 18-18. CAN Node Status
NS
Node Status
000
Not Active
010
Error Active
011
Error Warning Level
10X
Error Passive
11X
Bus Off
IRQ/IST
The IRQ bit and IST field indicate the interrupt source of the highest priority interrupt
currently pending and enabled in the CICENn register. Table 18-19 shows the several
interrupt codes when the encoding for all interrupt sources is enabled (CICEN = FFFFh).
Table 18-19. Highest Priority Interrupt Code
IRQ
IST3:0
CAN Interrupt Request
0
0000
No interrupt request
1
0000
Error interrupt
1
0001
Buffer 0
1
0010
Buffer 1
1
0011
Buffer 2
1
0100
Buffer 3
1
0101
Buffer 4
1
0110
Buffer 5
1
0111
Buffer 6
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