CP3BT23_14 Datasheet, PDF (176/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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19.5.5 Receive
At the receiver, the received data on the SRD pin is shifted into ARSR on the negative edge of SRCLK (or
SCK in synchronous mode), following the receive frame sync pulse, SRFS (or SFS in synchronous mode).
DMA Operation
When a complete data word has been received through the SRD pin, the new data word is copied to the
receive DMA register 0 (ARDR0). A DMA request is asserted when the ARDR0 register is full. If a new
data word is received while the ARDR0 register is still full, the ARDR0 register will be overwritten with the
new data.
FIFO Operation
When a complete word has been received, it is transferred to the receive FIFO at the current location of
the Receive FIFO Write Pointer (RWP). Then, the RWP is automatically incremented by 1.
A read from the Audio Receive FIFO Register (ARFR) results in a read from the receive FIFO at the
current location of the Receive FIFO Read Pointer (RRP). After every read operation from the receive
FIFO, the RRP is automatically incremented by 1.
When the RRP is equal to the RWP and the last access to the FIFO was a copy operation from the ARFR,
the receive FIFO is full. When a new complete data word has been shifted into ARSR while the receive
FIFO was already full, the shift register overruns. In this case, the new data in the ARSR will not be copied
into the FIFO and the RWP will not be incremented. A receive FIFO overrun is indicated by the RXO bit in
the Audio Interface Receive Status and Control Register (ARSCR). No receive interrupt will be generated
(even if enabled).
When the RWP is equal to the RRP and the last access to the receive FIFO was a read from the ARFR, a
receive FIFO underrun has occurred. This error condition is not prevented by hardware. Software must
ensure that no receive underrun occurs.
The receive frame synchronization pulse on the SRFS pin (or SFS in synchronous mode) and the receive
shift clock on the SRCLK (or SCK in synchronous mode) may be generated internally, or they can be
supplied by an external source.
19.5.6 Network Mode
In network mode, each frame sync signal marks the beginning of new frame. Each frame can consist of up
to four slots. The audio interface operates in a similar way to normal mode, however, in network mode the
transmitter and receiver can be assigned to specific slots within each frame as described below.
19.5.7 Transmit
The transmitter only shifts out data during the assigned slot. During all other slots the STD output is in
TRI-STATE mode.
DMA Operation
When a complete data word has been transmitted through the STD pin, a new data word is reloaded from
the corresponding transmit DMA register n (ATDRn). A DMA request is asserted when ATDRn is empty. If
a new data word must be transmitted in a slot n while ATDRn is still empty, the previous slot n data will be
retransmitted.
176 Advanced Audio Interface
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