CP3BT23_14 Datasheet, PDF (184/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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DWL
LPB
SCS
The Data Word Length bit controls whether the transferred data word has a length of 8 or 16
bits. After reset, the DWL bit is clear, so 8bit data words are used by default.
0 – 8-bit data word length.
1 – 16-bit data word length.
The Loop Back bit enables the loop back mode. In this mode, the SRD and STD pins are
internally connected. After reset the LPB bit is clear, so by default the loop back mode is
disabled.
0 – Loop back mode disabled.
1 – Loop back mode enabled
The Slot Count Select field specifies the number of slots within each frame. If the number of
slots per frame is equal to 1, the audio interface operates in normal mode. If the number of
slots per frame is greater than 1, the interface operates in network mode. After reset all SCS
bits are cleared, so by default the audio interface operates in normal mode.
SCS
00
0
10
11
Table 19-2.
Number of Slots per Frame
2
3
4
Mode
Normal mode
Network mode
Network mode
Network mode
IEFS
FSS
IEBC
CRF
CTF
FSL
The Internal/External Frame Sync bit controls, whether the frame sync signal for the receiver
and transmitter are generated internally or provided from an external source. After reset, the
IEFS bit is clear, so the frame synchronization signals are generated internally by default.
0 – Internal frame synchronization signal.
1 – External frame synchronization signal.
The Frame Sync Select bit controls whether the interface (receiver and transmitter) uses long
or short frame synchronization signals. After reset the FSS bit is clear, so short frame
synchronization signals are used by default.
0 – Short (bit length) frame synchronization signal.
1 – Long (word length) frame synchronization signal.
The Internal/External Bit Clock bit controls whether the bit clocks for receiver and transmitter
are generated internally or provided from an external source. After reset, the IEBC bit is
clear, so the bit clocks are generated internally by default.
0 – Internal bit clock.
1 – External bit clock.
The Clear Receive FIFO bit is used to clear the receive FIFO. When this bit is written with a
1, all pointers of the receive FIFO are set to their reset state. After updating the pointers, the
CRF bit will automatically be cleared again.
0 – Writing 0 has no effect.
1 – Writing 1 clears the receive FIFO.
The Clear Transmit FIFO bit is used to clear the transmit FIFO. When this bit is written with a
1, all pointers of the transmit FIFO are set to their reset state. After updating the pointers, the
CTF bit will automatically be cleared again.
0 – Writing 0 has no effect.
1 – Writing 1 clears the transmit FIFO.
The Frame Sync Length field specifies the length of the frame synchronization signal, when a
long frame sync signal (FSS = 1) and a 16-bit data word length (DWL = 1) are used. If an 8-
bit data word length is used, long frame syncs are always 6 bit clocks in length.
184 Advanced Audio Interface
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