CP3BT23_14 Datasheet, PDF (168/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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19 Advanced Audio Interface
The Advanced Audio Interface (AAI) provides a serial synchronous, full duplex interface to codecs and
similar serial devices. The transmit and receive paths may operate asynchronously with respect to each
other. Each path uses a 3wire interface consisting of a bit clock, a frame synchronization signal, and a
data signal.
The CPU interface can be either interrupt-driven or DMA. If the interface is configured for interrupt-driven
I/O, data is buffered in the receive and transmit FIFOs. If the interface is configured for DMA, the data is
buffered in registers.
The AAI is functionally similar to a MotorolaTM Synchronous Serial Interface (SSI). Compared to a
standard SSI implementation, the AAI interface does not support the so-called “On-demand Mode”. It also
does not allow gating of the shift clocks, so the receive and transmit shift clocks are always active while
the AAI is enabled. The AAI also does not support 12and 24-bit data word length or more than 4 slots
(words) per frame. The reduction of supported modes is acceptable, because the main purpose of the AAI
is to connect to audio codecs, rather than to other processors (DSPs).
The implementation of a FIFO as a 16-word receive and transmit buffer is an additional feature, which
simplifies communication and reduces interrupt load. Independent DMA is provided for each of the four
supported audio channels (slots). The AAI also provides special features and operating modes to simplify
gain control in an external codec and to connect to an ISDN controller through an IOM-2 compatible
interface.
19.1 AUDIO INTERFACE SIGNALS
19.1.1 Serial Transmit Data (STD)
The STD pin is used to transmit data from the serial transmit shift register (ATSR). The STD pin is an
output when data is being transmitted and is in high-impedance mode when no data is being transmitted.
The data on the STD pin changes on the positive edge of the transmit shift clock (SCK). The STD pin
goes into high-impedance mode on the negative edge of SCK of the last bit of the data word to be
transmitted, assuming no other data word follows immediately. If another data word follows immediately,
the STD pin remains active rather than going to the high-impedance mode.
19.1.2 Serial Transmit Clock (SCK)
The SCK pin is a bidirectional signal that provides the serial shift clock. In asynchronous mode, this clock
is used only by the transmitter to shift out data on the positive edge. The serial shift clock may be
generated internally or it may be provided by an external clock source. In synchronous mode, the SCK pin
is used by both the transmitter and the receiver. Data is shifted out from the STD pin on the positive edge,
and data is sampled on the SRD pin on the negative edge.
19.1.3 Serial Transmit Frame Sync (SFS)
The SFS pin is a bidirectional signal which provides frame synchronization. In asynchronous mode, this
signal is used as frame sync only by the transmitter. In synchronous mode, this signal is used as frame
sync by both the transmitter and receiver. The frame sync signal may be generated internally, or it may be
provided by an external source.
19.1.4 Serial Receive Data (SRD)
The SRD pin is used as an input when data is shifted into the Audio Receive Shift Register (ARSR). In
asynchronous mode, data on the SRD pin is sampled on the negative edge of the serial receive shift clock
(SRCLK). In synchronous mode, data on the SRD pin is sampled on the negative edge of the serial shift
clock (SCK). The data is shifted into ARSR with the most significant bit (MSB) first.
168 Advanced Audio Interface
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