CP3BT23_14 Datasheet, PDF (283/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
Bluetooth LLC
Registers
LINK_TIMER_ADJUST
_ PLUS
LINK_TIMER_ADJUST
_ MINUS
SLOTTIMER_WR_RD
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Table 28-1. Bluetooth LLC Registers (continued)
7
6
5
4
3
2
1
0
LINKTIMER_ADJUST_PLUS[7:0]
LINKTIMER_ADJUST_MINUS[7:0]
Reserved
SLOT_TIMER_WR_RD[5:0]
Table 28-2. CAN Control/ Status
CAN Control/
Status
CGCRn
CTIMn
GMSKBn
GMSKXn
BMSKBn
BMSKXn
CIENn
CIPNDn
CICLRn
CICENn
CSTPNDn
CANECn
CEDIAGn
CTMRn
15
14
13
12
11
10
9
8
7
6
Reserved
EI EN
EI PND
EI CLR
EI CEN
Res. DRI VE MON
EIT DIAG EN INTERN LOOP IGN ACK LO
AL
BACK
PSC[6:0]
SJW[1:0]
GM[28:18]
GM[14:0]
BM[28:18]
BM[14:0]
IEN[14:0]
IPND[14:0]
ICLR[14:0]
ICEN[14:0]
Reserved
NS[2:0]
REC[7:0]
CRC STU FF TXE
EBID[5:0]
CTMR[15:0]
5
4
3
DD IR TST PEN BUFF
LOCK
TSEG1[3:0]
RTR
IDE
RTR
IDE
IRQ
TEC[7:0]
2
1
0
CRX
CTX CAN EN
TSEG2[2:0]
GM[17:15]
XRTR
BM[17:15]
XRTR
IST[3:0]
EFID[3:0]
Table 28-3. CAN Memory Registers
CAN Memory
Registers
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CMBn.ID1
X128 X127 ID9 X126 ID8 X125 ID7 X124 ID6 X123 ID5 X122 ID4 X121 ID3 X120 ID2 XI19 ID1 XI18 ID0 SRR
IDE
XI17
XI16
XI15
ID10
RTR
CMBn.ID0
XI14
XI13
XI12
XI11
XI10
XI9
XI8
XI7
XI6
XI5
XI4
XI3
XI2
XI1
XI0
RTR
CMBn.DATA0 Data 1.7 Data 1.6 Data 1.5 Data 1.4 Data 1.3 Data 1.2 Data 1.1 Data 1 Data 2.7 Data 2.6 Data 2.5 Data 2.4 Data 2.3 Data 2.2 Data 2.1 Data 2
CMBn.DATA1 Data 3.7 Data 3.6 Data 3.5 Data 3.4 Data 3.3 Data 3.2 Data 3.1 Data 3 Data 4.7 Data 4.6 Data 4.5 Data 4.4 Data 4.3 Data 4.2 Data 4.1 Data 4
CMBn.DATA2 Data 5.7 Data 5.6 Data 5.5 Data 5.4 Data 5.3 Data 5.2 Data 5.1 Data 5 Data 6.7 Data 6.6 Data 6.5 Data 6.4 Data 6.3 Data 6.2 Data 6.1 Data 6
CMBn.DATA3 Data 7.7 Data 7.6 Data 7.5 Data 7.4 Data 7.3 Data 7.2 Data 7.1 Data 7 Data 8.7 Data 8.6 Data 8.5 Data 8.4 Data 8.3 Data 8.2 Data 8.1 Data 8
CMBn.TSTP TSTP 15 TSTP 14 TSTP 13 TSTP 12 TSTP 11 TSTP 10 TSTP 9 TSTP 8 TSTP 7 TSTP 6 TSTP 5 TSTP 4 TSTP 3 TSTP 2 TSTP 1 TSTP 0
CMBn.CNTSTAT DLC3 DLC2 DLC1 DLC0
Reserved
PRI3 PRI2 PRI1 PRI0
ST3
ST2
ST1
ST0
Table 28-4. DMAC Registers
DMAC Registers
ADCA
ADRA
ADCB
ADRB
BLTC
BLTR
DMACNTL
DMASTAT
20..16
N/A
N/A
N/A
15
Res.
14
13
INCB
12
ADB
N/A
11
10
9
8
7
6
5
Device A Address Counter
Device A Address
Device B Address Counter
Device B Address
Block Length Counter
Block Length
INCA
ADA SW RQ Res.
OT
DIR
Reserved
4
3
2
1
0
IND TCS EOVR ETC CHEN
VLD CH AC OVR
TC
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