CP3BT23_14 Datasheet, PDF (122/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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18 CAN Module
Each of the two CAN modules provides a Full CAN class, CAN (Controller Area Network) serial bus
interface for low/ high speed applications. They support reception and transmission of extended frames
with a 29-bit identifier, standard frames with an 11-bit identifier, applications that require high speed (up to
1 MBit/s), and a low-speed CAN interface with CAN master capability. Data transfer between the CAN bus
and the CPU is handled by 15 message buffers, which can be individually configured as receive or
transmit buffers. Every message buffer includes a status/control register which provides information about
its current status and capabilities to configure the buffer. All message buffers are able to generate an
interrupt on the reception of a valid frame or the successful transmission of a frame. In addition, an
interrupt can be generated on bus errors.
An incoming message is only accepted if the message identifier passes one of two acceptance filtering
masks. The filtering mask can be configured to receive a single message ID for each buffer or a group of
IDs for each receive buffer. One of the buffers uses a separate message filtering procedure. This provides
the capability to establish a BASIC-CAN path. Remote transmission requests can be processed
automatically by automatic reconfiguration to a receiver after transmission or by automated transmit
scheduling upon reception. A priority decoder allows any buffer to have one of 16 transmit priorities
including the highest or lowest absolute priority, for a total of 240 different transmit priorities.
A decided bit time counter (16-bit wide) is provided to support real time applications. The contents of this
counter are captured into the message buffer RAM on reception or transmission. The counter can be
synchronized through the CAN network. This synchronization feature allows a reset of the counter after
the reception or transmission of a message in buffer 0.
Each CAN module is a fast CPU bus peripheral which allows single-cycle byte or word read/write access.
The CPU controls the CAN module by programming the registers in the CAN register block. This includes
initialization of the CAN baud rate, logic level of the CAN pins, and enable/disable of the CAN module. A
set of diagnostic features, such as loopback, listen only, and error identification, support development with
the CAN module and provide a sophisticated error management tool.
Each CAN module implements the following features:
• CAN specification 2.0B
– Standard data and remote frames
– Extended data and remote frames
– 0 to 8 bytes data length
– Programmable bit rate up to 1 Mbit/s
• 15 message buffers, each configurable as receive or transmit buffers
– Message buffers are 16-bit wide dual-port RAM
– One buffer may be used as a BASIC-CAN path
• Remote Frame support
– Automatic transmission after reception of a Remote Transmission Request (RTR)
– Auto receive after transmission of a RTR
• Acceptance filtering
– Two filtering capabilities: global acceptance mask and individual buffer identifiers
– One of the buffers uses an independent acceptance filtering procedure
• Programmable transmit priority
• Interrupt capability
– One interrupt vector for all message buffers (receive/ transmit/error)
– Each interrupt source can be enabled/disabled
• 16-bit counter with time stamp capability on successful reception or transmission of a message
• Power Save capabilities with programmable Wake-Up over the CAN bus (alternate source for the
Multi-Input Wake-Up module)
122 CAN Module
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