CP3BT23_14 Datasheet, PDF (261/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
If the duty cycle register (DTYCAPx) holds a value which is greater than the value held in the period
register (PERCAPx) the TIOx output will remain at the opposite of its default value which corresponds to a
duty cycle of 100%. If the duty cycle register (DTYCAPx) register holds a value of 00h, the TIOx output will
remain at the default value which corresponds to a duty cycle of 0%, in which case the value in the
PERCAPx register is irrelevant. This scheme allows the duty cycle to be programmed in a range from 0%
to 100%.
In order to allow fully synchronized updates of the period and duty cycle compare values, the PERCAPx
and DTYCAPx registers are double buffered when operating in PWM mode. Therefore, if software writes
to either the period or duty cycle register while either of the two PWM channels is enabled, the new value
will not take effect until the counter value matches the previous period value or the timer is stopped.
Reading the PERCAPx or DTYCAPx register will always return the most recent value written to it.
The counter registers can be written if both 8-bit counters are stopped. This allows software to preset the
counters before starting, which can be used to generate PWM output waveforms with a phase shift
relative to each other. If the counter is written with a value other than 00h, it will start incrementing from
that value. The TIOx output will remain at its default value until the first 00h to 01h transition of the counter
value occurs. If the counter is preset to values which are less than or equal to the value held in the period
register (PERCAPx) the counter will count up until a match between the counter value and the PERCAPx
register value occurs. The counter will then be cleared and continue counting up. Alternatively, the counter
may be written with a value which is greater than the value held in the period register. In that case the
counter will count up to FFh, then roll over to 00h. In any case, the TIOx pin always changes its state at
the 00h to 01h transition of the counter.
Software may only write to the COUNTx register if both TxRUN bits of a timer subsystem are clear. Any
writes to the counter register while either timer is running will be ignored.
The two I/O pins associated with a timer subsystem function as independent PWM outputs in the dual 8-
bit PWM mode. If a PWM timer is stopped using its associated MODE.TxRUN bit the following actions
result:
• The associated TIOx pin will return to its default value as defined by the IOxCTL.PxPOL bit.
• The counter will stop and will retain its last value.
• Any pending updates of the PERCAPx and DTYCAPx register will be completed.
• The prescaler counter will be stopped and reset if both MODE.TxRUN bits are cleared.
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