CP3BT23_14 Datasheet, PDF (243/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
RST
TC
T0INTE
WDLTD
FRZT0E
The Restart bit is used to reset Timer T0. When this bit is set, it forces the timer to reload the
value in the TWMT0 register on the next rising edge of the selected input clock. The RST bit
is reset automatically by the hardware on the same rising edge of the selected input clock.
Writing a 0 to this bit position has no effect. At reset, the non-reserved bits of the register are
cleared.
0 – Writing 0 has no effect.
1 – Writing 1 resets Timer T0.
The Terminal Count bit is set by hardware when the Timer T0 count reaches zero and is
cleared when software reads the T0CSR register. It is a read-only bit. Any data written to this
bit position is ignored. The TC bit is not cleared if FREEZE mode is asserted by an external
debugging system.
0 – Timer T0 did not count down to 0.
1 – Timer T0 counted down to 0.
The Timer T0 Interrupt Enable bit enables an interrupt to the CPU each time the Timer T0
count reaches zero. When this bit is clear, Timer T0 interrupts are disabled.
0 – Timer T0 interrupts disabled.
1 – Timer T0 interrupts enabled.
The Watchdog Last Touch Delay bit is set when either WDCNT or WDSDM is written and the
data transfer to the Watchdog is in progress (see WDCNT and WDSDM register description).
When clear, it is safe to switch to Power Save mode.
0 – No data transfer to the Watchdog is in progress, safe to enter Power Save mode.
1 – Data transfer to the Watchdog in progress.
The Freeze Timer0 Enable bit controls whether TImer 0 is stopped in FREEZE mode. If this
bit is set, the Timer 0 is frozen (stopped) when the FREEZE input to the TWM is asserted. If
the FRZT0E bit is clear, only the Watchdog timer is frozen by asserting the FREEZE input
signal. After reset, this bit is clear.
0 – Timer T0 unaffected by FREEZE mode.
1 – Timer T0 stopped in FREEZE mode.
24.4.5 Watchdog Count Register (WDCNT)
The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the
Watchdog counter each time the Watchdog is serviced. The Watchdog is started by the first write to this
register. Each successive write to this register restarts the Watchdog count with the written value. At reset,
this register is initialized to 0Fh.
7
0
PRESET
24.4.6 Watchdog Service Data Match Register (WDSDM)
The WSDSM register is a byte-wide, write-only register used for servicing the Watchdog. When this type
of servicing is enabled (TWCFG.WDSDME = 1), the Watchdog is serviced by writing the value 5Ch to the
WSDSM register. Each such servicing reloads the Watchdog counter with the value previously written to
the WDCNT register. Writing any data other than 5Ch triggers a Watchdog error. Writing to the register
more than once in one Watchdog clock cycle also triggers a Watchdog error signal. If this type of servicing
is disabled (TWCFG.WDSDME = 0), any write to the WSDSM register is ignored.
7
0
RSTDATA
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Timing and Watchdog Module 243