CP3BT23_14 Datasheet, PDF (267/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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CxEDG
000
001
010
011
100
101
110
111
Table 26-3.
Capture
Rising edge
Falling edge
Rising edge
Falling edge
Both edges
Both edges
Both edges
Both edges
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Counter Reset
No
No
Yes
Yes
No
Rising edge
Falling edge
Both edges
PxPOL
The PWM Polarity bit selects the output polarity. While operating in PWM mode the bit
specifies the polarity of the corresponding PWM output (TIOx). Once a counter is stopped,
the output will assume the value of PxPOL, i.e., its initial value. The PxPOL bit has no effect
while operating in capture mode.
0 – The PWM output goes high at the 00h to 01h transition of the counter and will go low
once the counter value matches the duty cycle value.
1 – The PWM output goes low at the 00h to 01h transition of the counter and will go high
once the counter value matches the duty cycle value.
26.2.3 I/O Control Register 2 (IO2CTL)
The IO2CTL register is a word-wide read/write register. The register controls the functionality of the I/O
pins TIO5 through TIO8 depending on the selected mode of operation. The register is cleared at reset.
7
6
4
3
2
0
P6POL
C6EDG
P5POL
C5EDG
15
14
12
11
10
8
P8POL
C8EDG
P7POL
C7EDG
The functionality of the bit fields of the IO2CTL register is identical to the ones described in the IO1CTL
register section.
26.2.4 Interrupt Control Register (INTCTL)
The INTCTL register is a word-wide read/write register. It contains the interrupt enable bits for all 16
interrupt sources of the VTU. Each interrupt enable bit corresponds to an interrupt pending bit located in
the Interrupt Pending Register (INTPND). All INTCTL register bits are solely under software control. The
register is clear after reset.
7
I2DEN
6
I2CEN
5
I2BEN
4
I2AEN
3
I1DEN
2
I1CEN
1
I1BEN
0
I1AEN
15
I4DEN
IxAEN
14
I4CEN
13
I4BEN
12
I4AEN
11
I3DEN
10
I3CEN
9
I3BEN
8
I3AEN
The Timer x Interrupt A Enable bit controls interrupt requests triggered on the corresponding
IxAPD bit being set. The associated IxAPD bit will be updated regardless of the value of the
IxAEN bit.
0 – Disable system interrupt request for the IxAPD pending bit.
1 – Enable system interrupt
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Versatile Timer Unit (VTU) 267