CP3BT23_14 Datasheet, PDF (316/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
www.ti.com
31 Revision History
Date
Major Changes From Previous Version
4/3/2003
Original release.
5/26/2003
Fixed maximum boot area in Section 8. Fixed names of clock signals in Figures 5 and 6. Fixed addresses of
FSMARx registers in Register Map section. Added default value for RNGDIV.
6/16/2003
Corrected Table 27. Changed IOH and IOL.
6/30/2003
Changed NSIDs, deleted commercial temperature range device, changed ADC conversion time to 15
microseconds.
10/7/2003
Updated DC electrical specifications. Added ADC electrical specifications. Added more detail to Table 7. Added
Table 25.
11/14/2003
Defined valid range of SCDV field in Microwire/SPI module. Noted default PRSSC register value generates a
Slow Clock frequency slightly higher than 32768Hz. Clarified usage of CVSTAT register bits and fields in
CVSD/PCM module. Updated layout of Bluetooth LLC registers. Added usage hint for avoiding ACCESS.bus
module bus error. Added usage hint for avoiding CAN unexpected loopback condition.
2/28/2004
Changed NSID designations in the product selection guide. Updated Bluetooth section for LMX5251 and
LMX5252 radio chips. Added BTSEQ[3:1] signals to pin descriptions, GPIO alternate functions, and package
pin assignments. Added entry for CTIM register in CAN section register list. Changed CVSD Conversion
section. Changed definition of the RESOLUTION field of the CVSD Control register (CVCTRL). Changed reset
values for ADC registers. Added maximum I/O voltage in Absolute Maximum Ratings section. Added RESET
Low minimum DC specification. Added Iccprog DC specification. Changed Vxl2 DC specification.
3/16/2004
Changed LMX5251 interface circuit. Updated DC specifications for clock input low voltage, reset input high
voltage, and halt current.
5/10/2004
Corrected NSIDs for no-lead solder parts.
5/12/2004
Moved revision history in front of physical dimensions. Changed back page disclaimers.
6/2/2004
Changed AC and DC specifications.
6/15/2004
Changed absolute maximum supply voltage to 3.6V. Changed Preliminary to Final.
7/16/2004
Added AC timing specifications for ACCESS.bus, external bus, GPIO, Microwire/SPI, and UART. Corrected
address of flash data memory in Section 8.
11/9/2004
Added conditions which clear the ACBST, ACBCST, and ACBCTL1 registers. Added external reset as
condition which clears WDRST and ISPRST bits in the MSTAT register. Inverted sense of PEN_DOWN bit in
the ADCRESLT register.
4/4/2005
Added new reset circuits. Added note about fluctuations in response due to SDI activity. New back page.
9/24/2006
Added 14-bit counter delay to external reset.
2/21/2007
Updated NSIDs.
1/22/14
Updated from National to TI format.
316 Revision History
Submit Documentation Feedback
Product Folder Links: CP3BT23
Copyright © 2013–2014, Texas Instruments Incorporated