CP3BT23_14 Datasheet, PDF (133/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
18.2.6 Bit Time Logic
In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured
by software. The CAN module divides a nominal bit time into three time segments: synchronization
segment, time segment 1 (TSEG1), and time segment 2 (TSEG2). Figure 18-11 shows the various
elements of a CAN bit time.
CAN Bit Time
The number of time quanta in a CAN bit (CAN Bit Time) ranges between 4 and 25. The sample point is
positioned between TSEG1 and TSEG2 and the transmission point is positioned at the end of TSEG2.
Figure 18-11. Bit Timing
TSEG1 includes the propagationsegment and the phase segment 1 as specified in the CAN specification
2.0B. The length of the time segment 1 in time quanta (tq) is defined by the TSEG1[3:0] bits.
TSEG2 represents the phase segment 2 as specified in the CAN specification 2.0B. The length of time
segment 2 in time quanta (tq) is defined by the TSEG2[3:0] bits.
The Synchronization Jump Width (SJW) defines the maximum number of time quanta (tq) by which a
received CAN bit can be shortened or lengthened in order to achieve resynchronization on “recessive” to
“dominant” data transitions on the bus. In the CAN implementation, the SJW must be configured less or
equal to TSEG1 or TSEG2, whichever is smaller.
Synchronization
A CAN device expects the transition of the data signal to be within the synchronization segment of each
CAN bit time. This segment has the fixed length of one time quantum.
However, two CAN nodes never operate at exactly the same clock rate, and the bus signal may deviate
from the ideal waveform due to the physical conditions of the network (bus length and load). To
compensate for the various delays within a network, the sample point can be positioned by programming
the length of TSEG1 and TSEG2 (see Figure 18-11).
In addition, two types of synchronization are supported. The BTL logic compares the incoming edge of a
CAN bit with the internal bit timing. The internal bit timing can be adapted by either hard or soft
synchronization (re-synchronization).
Hard synchronization is performed at the beginning of a new frame with the falling edge on the bus while
the bus is idle. This is interpreted as the SOF. It restarts the internal logic.
Soft synchronization is performed during the reception of a bit stream to lengthen or shorten the internal
bit time. Depending on the phase error (e), TSEG1 may be increased or TSEG2 may be decreased by a
specific value, the resynchronization jump width (SJW).
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