CP3BT23_14 Datasheet, PDF (80/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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1 – PLL is stable or disabled (CRCTRL.PLLPWD = 0). Figure 12-1. Power Mode State Diagram Some of
the power-up transitions are based on the occurrence of a wake-up event. An event of this type can be
either a maskable interrupt or a non-maskable interrupt (NMI). All of the maskable hardware wake-up
events are monitored by the Multi-Input Wake-Up (MIWU) Module, which is active in all modes. Once a
wake-up event is detected, it is latched until an interrupt acknowledge cycle occurs or a reset is applied. A
wake-up event causes a transition to the Active mode and restores normal clock operation, but does not
start execution of the program. It is the interrupt handler associated with the wake-up source (MIWU or
NMI) that causes program execution to resume.
12.7.1 Active Mode to Power Save Mode
A transition from Active mode to Power Save mode is performed by writing a 1 to the PMMCR.PSM bit.
The transition to Power Save mode is either initiated immediately or at execution of the next WAIT
instruction, depending on the state of the PMMCR.WBPSM bit.
For an immediate transition to Power Save mode (PMMCR.WBPSM = 0), the CPU continues to operate
using the low-frequency clock. The PMMCR.PSM bit becomes set when the transition to the Power Save
mode is completed.
For a transition at the next WAIT instruction (PMMCR.WBPSM = 1), the CPU continues to operate in
Active mode until it executes a WAIT instruction. At execution of the WAIT instruction, the device enters
the Power Save mode, and the CPU waits for the next interrupt event. In this case, the PMMCR.PSM bit
becomes set when it is written, even before the WAIT instruction is executed.
12.7.2 Entering Idle Mode
Entry into Idle mode is performed by writing a 1 to the PMMCR.IDLE bit and then executing a WAIT
instruction. The PMMCR.WBPSM bit must be set before the WAIT instruction is executed. Idle mode can
be entered only from the Active or Power Save mode.
12.7.3 Disabling the High-Frequency Clock
When the low-frequency oscillator is used to generate the Slow Clock, power consumption can be
reduced further in the Power Save or Idle mode by disabling the high-frequency oscillator. This is
accomplished by writing a 1 to the PMMCR.DHC bit before executing the WAIT instruction that puts the
device in the Power Save or Idle mode. The highfrequency clock is turned off only after the device enters
the Power Save or Idle mode.
The CPU operates on the low-frequency clock in Power Save mode. It can turn off the high-frequency
clock at any time by writing a 1 to the PMMCR.DHC bit. The high-frequency oscillator is always enabled in
Active mode and always disabled in Halt mode, without regard to the PMMCR.DHC bit setting.
Immediately after power-up and entry into Active mode, software must wait for the low-frequency clock to
become stable before it can put the device in Power Save mode. It should monitor the PMMSR.OLC bit
for this purpose. Once this bit is set, Slow Clock is stable and Power Save mode can be entered.
12.7.4 Entering Halt Mode
Entry into Halt mode is accomplished by writing a 1 to the PMMCR.HALT bit and then executing a WAIT
instruction. The PMMCR.WBPSM bit must be set before the WAIT instruction is executed. Halt mode can
be entered only from Active or Power Save mode.
80
Power Management
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