CP3BT23_14 Datasheet, PDF (47/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
8.5.10 Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN)
The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase
transition times. Software must not modify this register while program/erase operation is in progress
(FMBUSY set). At reset, this register is initialized to 30h if the flash memory is idle. The CPU bus master
has read/write access to this register.
7
0
FTTRAN
FTTRAN
The Flash Timing Transition Count field specifies a delay of (FTTRAN + 1) prescaler output
clocks.
8.5.11 Flash Memory Programming Time Reload Register (FMPROG/FSMPROG)
The FMPROG/FSMPROG register is a byte-wide read/write register that controls the programming pulse
width. Software must not modify this register while a program/erase operation is in progress (FMBUSY
set). At reset, this register is initialized to 16h if the flash memory is idle. The CPU bus master has
read/write access to this register.
7
0
FTPROG
FTPROG
The Flash Timing Programming Pulse Width field specifies a programming pulse width of 8
× (FTPROG + 1) prescaler output clocks.
8.5.12 Flash Memory Page Erase Time Reload Register (FMPERASE/FSMPERASE)
The FMPERASE/FSMPERASE register is a byte-wide read/write register that controls the page erase
pulse width. Software must not modify this register while a program/ erase operation is in progress
(FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master
has read/write access to this register.
7
0
FTPER
FTPER
The Flash Timing Page Erase Pulse Width field specifies a page erase pulse width of 4096
x (FTPER + 1) prescaler output clocks.
8.5.13 Flash Memory Module Erase Time Reload Register 0 (FMMERASE0/FSMMERASE0)
The FMMERASE0/FSMMERASE0 register is a byte-wide read/write register that controls the module
erase pulse width. Software must not modify this register while a program/erase operation is in progress
(FMBUSY set). At reset, this register is initialized to EAh if the flash memory is idle. The CPU bus master
has read/write access to this register.
7
0
FTMER
FTMER
xThe Flash Timing Module Erase Pulse Width field specifies a module erase pulse width of
4096 X (FTMER + 1) prescaler output clocks.
Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CP3BT23
Flash Memory
47