CP3BT23_14 Datasheet, PDF (178/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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FIFO Operation
When a complete word has been received, it is transferred to the receive FIFO at the current location of
the Receive FIFO Write Pointer (RWP). After that, the RWP is automatically incremented by 1. Therefore,
data received in the next slot is copied to the next higher FIFO location.
A read from the Audio Receive FIFO Register (ARFR) results in a read from the receive FIFO at the
current location of the Receive FIFO Read Pointer (RRP). After every read operation from the receive
FIFO, the RRP is automatically incremented by 1.
When the RRP is equal to the RWP and the last access to the FIFO was a transfer to the ARFR, the
receive FIFO is full. When a new complete data word has been shifted into the ARSR while the receive
FIFO was already full, the shift register overruns. In this case, the new data in the ARSR will not be
transferred to the FIFO and the RWP will not be incremented. A receive FIFO overrun is indicated by the
RXO bit in the Audio Interface Receive Status and Control Register (ARSCR). No receive interrupt will be
generated (even if enabled).
When the current RWP is equal to the TWP and the last access to the receive FIFO was a read from
ARFR, a receive FIFO underrun has occurred. This error condition is not prevented by hardware. Software
must ensure that no receive underrun occurs.
The receive frame synchronization pulse on the SRFS pin (or SFS in synchronous mode) and the receive
shift clock on the SRCLK (or SCK in synchronous mode) may be generated internally, or they can be
supplied by an external source
19.6 Communication Options
19.6.1 Data Word Length
The word length of the audio data can be selected to be either 8 or 16 bits. In 16-bit mode, all 16 bits of
the transmit and receive shift registers (ATSR and ARSR) are used. In 8bit mode, only the lower 8 bits of
the transmit and receive shift registers (ATSR and ARSR) are used.
19.6.2 Frame Sync Signal
The audio interface can be configured to use either long or short frame sync signals to mark the beginning
of a new data frame. If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status
register is clear, the receive and/or transmit path generates or recognizes short frame sync pulses with a
length of one bit shift clock period. When these short frame sync pulses are used, the transfer of the first
data bit or the first slot begins at the first positive edge of the shift clock after the negative edge on the
frame sync pulse.
If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status register is set, the
receive and/or transmit path generates or recognizes long frame sync pulses. For 8-bit data, the frame
sync pulse generated will be 6 bit shift clock periods long, and for 16-bit data the frame sync pulse can be
configured to be 13, 14, 15, or 16 bit shift clock periods long. When receiving frame sync, it should be
active on the first bit of data and stay active for a least two bit clock periods. It must go low for at least one
bit clock period before starting a new frame. When long frame sync pulses are used, the transfer of the
first word (first slot) begins at the first positive edge of the bit shift clock after the positive edge of the
frame sync pulse. Figure 19-7 shows examples of short and long frame sync pulses. Some codecs require
an inverted frame sync signal. This is available by setting the Inverted Frame Sync bit in the AGCR
register.
178 Advanced Audio Interface
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