CP3BT23_14 Datasheet, PDF (142/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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To answer Remote Frames, the CPU writes TX_RTR in the buffer status register, which causes the buffer
to wait for a remote frame. When a remote frame passes the acceptance filtering mask of one or more
buffers, the buffer status will change to TX_ONCE_RTR, the contents of the buffer will be transmitted, and
afterwards the CAN module will write TX_RTR in the status code register again.
If the CPU writes TX_ONCE_RTR into the buffer status, the contents of the buffer will be transmitted, and
the successful transmission the buffer goes into the “wait for Remote Frame” condition TX_RTR.
18.6.1 Transmit Scheduling
After writing TX_ONCE into the buffer status, the transmission process begins and the BUSY bit is set. As
soon as a buffer gets the TX_BUSY status, the buffer is no longer accessible by the CPU except for the
ST[3:1] bits of the CNSTAT register. Starting with the beginning of the CRC field of the current frame, the
CAN module looks for another buffer transmit request and selects the buffer with the highest priority for
the next transmission by changing the buffer state from TX_ONCE to TX_BUSY. This transmit request
can be canceled by the CPU or can be overwritten by another transmit request of a buffer with a higher
priority as long as the transmission of the next frame has not yet started. This means that between the
beginning of the CRC field of the current frame and the transmission start of the next frame, two buffers,
the current buffer and the buffer scheduled for the next transmission, are in the BUSY status. To cancel
the transmit request of the next frame, the CPU must change the buffer state to TX_NOT_ACTIVE. When
the transmit request has been overwritten by another request of a higher priority buffer, the CAN module
changes the buffer state from TX_BUSY to TX_ONCE. Therefore, the transmit request remains pending.
Figure 18-23 further illustrates the transmit timing.
BUS
BUS
IDLE
SOF
1 BIT
ARBITRATION FIELD
+ CONTROL
12/29 BIT + 6 BIT
DATA FIELD
(IF PRESENT)
n × 8 BIT
CRC
FIELD
16 BIT
ACK
FIELD
2 BIT
EOF
7 BIT
IFS
3 BIT
TX_BUSY
current buffer
TX_BUSY
next buffer
CPU write TX_ONCE
in buffer status
Begin selection of next buffer
if new tx_request
DS040
Figure 18-23. Data Transmission
If the transmit process fails or the arbitration is lost, the transmission process will be stopped and will
continue after the interrupting reception or the error signaling has finished (see Figure 18-23). In that case,
a new buffer select follows and the TX process is executed again. Note: The canceled message can be
delayed by a TX request of a buffer with a higher priority. While TX_BUSY is high, software cannot
change the contents of the message buffer object. In all cases, writing to the BUSY bit will be ignored.
Note: The canceled message can be delayed by a TX request of a buffer with a higher priority. While
TX_BUSY is high, software cannot change the contents of the message buffer object. In all cases, writing
to the BUSY bit will be ignored.
142 CAN Module
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