CP3BT23_14 Datasheet, PDF (187/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
19.7.7 Audio Receive Status and Control Register (ARSCR)
The ARSCR register is used to control the operation of the receiver path of the audio interface. It also
holds bits which report the current status of the receive FIFO. The CPU bus master has read/write access
to the ASCR register. At reset, this register is loaded with 0004h.
7
4
3
2
1
0
RXSA
RXO
RXE
RXF
RXAF
15
12
11
8
RXFWL
RXDSA
RXAF
RXF
RXE
RXO
RXSA
The Receive Buffer Almost Full bit is set when the number of data bytes/words in the receive
buffer is equal to the specified warning limit.
0 – Receive FIFO below warning limit.
1 – Receive FIFO is almost full.
The Receive Buffer Full bit is set when the receive buffer is full. The RXF bit is set when the
RWP is equal to the RRP and the last access was a write to the FIFO.
0 – Receive FIFO is not full.
1 – Receive FIFO full.
The Receive Buffer Empty bit is set when the the RRP is equal to the RWP and the last
access to the FIFO was a read operation (read from ARDR).
0 – Receive FIFO is not empty.
1 – Receive FIFO is empty.
The Receive Overflow bit indicates that a receive shift register has overrun. This occurs,
when a completed data word has been shifted e receive FIFO was already full (the RXF bit
was set). In this case, the new data in ARSR will not be copied into the FIFO and the RWP
will not be incremented. Also, no receive interrupt and DMA request will generated (even if
enabled).
0 – No overflow has occurred.
1 – Overflow has occurred.
The Receive Slot Assignment field specifies which slots are recognized by the receiver of the
audio interface. Multiple slots may be enabled. If the frame consists of less than 4 slots, the
RXSA bits for unused slots are ignored. For example, if a frame only consists of 2 slots,
RXSA bits 2 and 3 are ignored.
The following table shows the slot assignment scheme.
RXSA Bit
RXSA0
RXSA1
RXSA2
RXSA3
Table 19-4.
Slots Enabled
0
1
2
3
After reset the RXSA field is clear, so software must load the correct slot assignment.
RXDSA
The Receive DMA Slot Assignment field specifies which slots (audio channels) are supported
by DMA. If the RXDSA bit is set for an assigned slot n (RXSAn = 1), the data received within
this slot will not be transferred into the receive FIFO, but will instead be written into the
corresponding Receive DMA data register (ARDRn). A DMA request n is asserted, when the
ARDRn is full and if the RMA bit n is set. If the RXSD bit for a slot is clear, the RXDSA bit is
ignored. The following table shows the DMA slot assignment scheme.
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