CP3BT23_14 Datasheet, PDF (9/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
3.20 POWER MANAGEMENT
The Power Management Module (PMM) improves the efficiency of the device by changing the operating
mode and power consumption to match the required level of activity.
The device can operate in any of four power modes:
• Active: The device operates at full speed using the high-frequency clock. All device functions are fully
operational
• Power Save: The device operates at reduced speed using the Slow Clock. The CPU and some
modules can continue to operate at this low speed.
• Idle: The device is inactive except for the Power Management Module and Timing and Watchdog
Module, which continue to operate using the Slow Clock.
• Halt: The device is inactive but still retains its internal state (RAM and register contents).
3.21 DMA CONTROLLER
The Direct Memory Access Controller (DMAC) can speed up data transfer between memory and I/O
devices or between two memories, relative to data transfers performed directly by the CPU. A method
called cycle-stealing allows the CPU and the DMAC to share the CPU bus efficiently. The DMAC
implements four independent DMA channels. DMA requests from a primary and a secondary source are
recognized for each DMA channel, as well as a software DMA request issued directly by the CPU.
Table 3-1 shows the DMA channel assignment on the CP3BT23 architecture. The following on-chip
modules can assert a DMA request to the DMAC:
• CR16C (Software DMA request)
• USART
• Advanced Audio Interface
• CVSD/PCM Converter
Channel
0 (Primary)
0 (Secondary)
1 (Primary)
1 (Secondary)
2 (Primary)
2 (Secondary)
3 (Primary)
3 (Secondary)
Table 3-1. DMA Channel Assignment
Peripheral
N/A
USART
USART
Reserved
Audio Interface
CVSD/PCM Transcoder
Audio Interface
CVSD/PCM Transcoder
Transaction
Reserved
R
W
N/A
R
R
W
W
Register
N/A
RX
TXBUF
N/A
ARDR0
PCMOUT
ATDR0
PCMIN
The interface can handle data words of either 8or 16-bit length and data frames can consist of up to four
slots.
In the normal mode of operation, the interface only transfers one word at a periodic rate. In the network
mode, the interface transfers multiple words at a periodic rate. The periodic rate is also called a data
frame and each word within one frame is called a slot. The beginning of each new data frame is marked
by the frame sync signal.
Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CP3BT23
Device Overview
9