CP3BT23_14 Datasheet, PDF (188/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
RXDSA Bit
RXDSA0
RXDSA1
RXDSA2
RXDSA3
Table 19-5.
Slots Enabled for DMA
0
1
2
3
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RXFWL
The Receive FIFO Warning Level field specifies when a receive interrupt is asserted. A
receive interrupt is asserted, when the number of bytes/words in the receive FIFO is greater
than the warning level value. An RXFWL value of 0 means that a receive interrupt is
asserted if one or more bytes/words are in the RX FIFO. After reset, the RXFWL bit is clear.
19.7.8 Audio Transmit Status and Control Register (ATSCR)
The ASCR register controls the basic operation of the interface. It also holds bits which report the current
status of the audio communication. The CPU bus master has read/write access to the ASCR register. At
reset, this register is loaded with F003h.
7
4
3
2
1
0
TXSA
TXU
TXF
TXE
TXAE
15
TXAE
TXE
TXF
TXU
TXSA
12
11
8
TXFWL
TXDSA
The Transmit FIFO Almost Empty bit is set when the number of data bytes/words in transmit
buffer is equal to the specified warning limit.
0 – Transmit FIFO above warning limit.
1 – Transmit FIFO at or below warning limit.
The Transmit FIFO Empty bit is set when the transmit buffer is empty. The TXE bit is set to
one every time the TRP is equal to the TWP and the last access to the FIFO was read
operation (into ATSR).
0 – Transmit FIFO not empty.
1 – Transmit FIFO empty.
The Transmit FIFO Full bit is set when the TWP is equal to the TRP and the last access to
the FIFO was write operation (write to ATDR).
0 – Transmit FIFO not full.
1 – Transmit FIFO full.
The Transmit Underflow bit indicates that the transmit shift register (ATSR) has underrun.
This occurs when the transmit FIFO was already empty and a complete data word has been
transferred. In this case, the TRP will be decremented by 1 and the previous data will be
retransmitted. No transmit interrupt and no DMA request will be generated (even if enabled).
0 – Transmit underrun occurred.
1 – Transmit underrun did not occur.
The Transmit Slot Assignment field specifies during which slots the transmitter is active and
drives data through the STD pin. The STD pin is in high impedance state during all other
slots. If the frame consists of less than 4 slots, the TXSA bits for unused slots are ignored.
For example, if a frame only consists of 2 slots, TXSA bits 2 and 3 are ignored. The following
table shows the slot assignment scheme.
188 Advanced Audio Interface
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