CP3BT23_14 Datasheet, PDF (234/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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SDAST
SLVSTP
The SDA Status bit indicates that the SDA data register is waiting for data (transmit, as
master or slave) or holds data that should be read (receive, as master or slave). This bit is
cleared when reading from the ACBSDA register during a receive, or when written to during
a transmit. When the ACBCTL1.START bit is set, reading the ACBSDA register does not
clear the SDAST bit. This enables the ACB to send a repeated start in master receive mode.
0 – ACB module is not waiting for data transfer.
1 – ACB module is waiting for data to be loaded or unloaded.
The Slave Stop bit indicates that a Stop Condition was detected after a slave transfer (i.e.,
after a slave transfer in which MATCH or GCMATCH is set). Writing 1 to SLVSTP clears it. It
is also cleared when the module is disabled. Writing 0 to SLVSTP is ignored.
0 – No stop condition after slave transfer occurred.
1 – Stop condition after slave transfer occurred.
23.3.3 ACB Control Status Register (ACBCST)
The ACBCST register is a byte-wide, read/write register that maintains current ACB status. When reset,
disabled, or in Halt or Idle modes, the non-reserved bits of ACBCST are cleared.
7
6
Reserved
5
4
3
2
1
TGSCL
TSDA
GCMTCH
MATCH
BB
0
BUSY
BUSY
The BUSY bit indicates that the ACB module is:
• Generating a Start Condition
• In Master mode (ACBST.MASTER is set)
• In Slave mode (ACBCST.MATCH or ACBCST.GCMTCH is set)
• In the period between detecting a Start and completing the reception of the address byte.
After this, the ACB either becomes not busy or enters slave mode.
The BUSY bit is cleared by the completion of any of the above states, and by disabling the
module. BUSY is a read only bit. It must always be written with 0.
0 – ACB module is not busy.
1 – ACB module is busy.
BB
The Bus Busy bit indicates the bus is busy. It is set when the bus is active (i.e., a low level
on either SDA or SCL) or by a Start Condition. It is cleared when the module is disabled, on
detection of a Stop Condition, or when writing 1 to this bit. See “Usage Hints” for a
description of the use of this bit. This bit should be set when either the SDA or SCL signals
are low. This is done by sampling the SDA and SCL signals continuously and setting the bit if
one of them is low. The bit remains set until cleared by a STOP condition or written with 1.
0 – Bus is not busy.
1 – Bus is busy.
MATCH
The Address Match bit indicates in slave mode when ACBADDR.SAEN is set and the first
seven bits of the address byte (the first byte transferred after a Start Condition) matches the
7-bit address in the ACBADDR register, or when ACBADDR2.SAEN is set and the first seven
bits of the address byte matches the 7-bit address in the ACBADDR2 register. It is cleared
by Start Condition or repeated Start and Stop Condition (including illegal Start or Stop
Condition).
0 – No address match occurred.
1 – Address match occurred.
GCMTCH
The Global Call Match bit is set in slave mode when the ACBCTL1.GCMEN bit is set and the
address byte (the first byte transferred after a Start Condition) is 00h. It is cleared by a Start
Condition or repeated Start and Stop Condition (including illegal Start or Stop Condition).
0 – No global call match occurred.
1 – Global call match occurred.
234 ACCESS.bus Interface
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