CP3BT23_14 Datasheet, PDF (54/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Continuation
When the BLTCn counter reaches 0:
1. The contents of the ADRAn, ADRBn, and BLTRn registers are copied to the ADCAn, ADCBn, and
BLTCn counters.
2. The DMAC channel checks the value of the DMAS-TAT.TC bit.
If the DMASTAT.TC bit is set:
1. The DMASTAT.OVR bit is set.
2. A level interrupt is generated if enabled by the DMACNTLn.EOVR bit.
3. The operation is repeated.
If the DMASTAT.TC bit is clear:
1. The DMASTAT.TC bit is set.
2. A level interrupt is generated if enabled by the DMACNTLn.ETC bit.
3. The DMAC operation is repeated.
Termination
The DMA transfer is terminated when the DMACNTLn.CHEN bit is cleared.
9.4 SOFTWARE DMA REQUEST
In addition to the hardware requests from I/O devices, a DMA transfer request can also be initiated by
software. A software DMA transfer request must be used for block copying between memory devices.
When the DMACNTLn.SWRQ bit is set, the corresponding DMA channel receives a DMA transfer request.
When the DMACNTLn.SWRQ bit is clear, the software DMA transfer request of the corresponding channel
is inactive.
For each channel, use the software DMA transfer request only when the corresponding hardware DMA
request is inactive and no terminal count interrupt is pending. Software can poll the DMASTAT.CHAC bit
to determine whether the DMA channel is already active. After verifying the DMASTATn.CHAC bit is clear
(channel inactive), check the DMASTATn.TC (terminal count) bit. If the TC bit is clear, then no terminal
count condition exists and therefore no terminal count interrupt is pending. If the channel is not active and
no terminal count interrupt is pending, software may request a DMA transfer.
9.5 DEBUG MODE
When the FREEZE signal is active, all DMA operations are stopped. They will start again when the
FREEZE signal goes inactive. This allows breakpoints to be used in debug systems.
9.6 DMA CONTROLLER REGISTER SET
There are four identical sets of DMA controller registers, as listed in Table 9-2.
Name
ADCA0
ADRA0
ADCB0
ADRB0
BLTC0
BLTR0
DMACNTL0
DMASTAT0
Table 9-2. DMA Controller Registers
Address
FF F800h
FF F804h
FF F808h
FF F80Ch
FF F810h
FF F814h
FF F81Ch
FF F81Eh
Description
Device A Address Counter Register
Device A Address Register
Device B Address Counter Register
Device B Address Register
Block Length Counter Register
Block Length Register
DMA Control Register
DMA Status Register
54
DMA Controller
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