CP3BT23_14 Datasheet, PDF (27/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Table 6-2. Operating Environment Selection
EMPTY
No
No
N/A
N/A
N/A
Yes
Yes
Operating Environment
Internal ROM enabled (IRE) mode
External ROM enabled (ERE) mode
Development (DEV) mode
Development (DEVINT) mode with internal memory
In-System-Programming (ISP) mode
In-System-Programming (ISP) mode
In-System-Programming (ISP) mode
6.2 BUS INTERFACE UNIT (BIU)
The BIU controls the interface between the CPU core bus and those on-chip modules which are mapped
into BIU zones. These on-chip modules are the flash program memory and the I/O zone. The BIU controls
the configured parameters for bus access (such as the number of wait states for memory access) and
issues the appropriate bus signals for the requested access.
6.3 BUS CYCLES
There are four types of data transfer bus cycles:
• Normal read
• Fast read
• Early write
• Late write
The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a
read), the type of memory or I/O being accessed, and the access type programmed into the BIU control
registers (early/late write or normal/fast read).
For read operations, a basic normal read takes two clock cycles, and a fast-read bus cycle takes one
clock cycle. Normal read bus cycles are enabled by default after reset.
For write operations, a basic late-write bus cycle takes two clock cycles, and a basic early-write bus cycle
takes three clock cycles. Early-write bus cycles are enabled by default after reset. However, late-write bus
cycles are needed for ordinary write operations, so this configuration must be changed by software (see
Section 6.4.1).
In certain cases, one or more additional clock cycles are added to a bus access cycle. There are two
types of additional clock cycles for ordinary memory accesses, called internal wait cycles (TIW) and hold
(Thold) cycles.
A wait cycle is inserted in a bus cycle just after the memory address has been placed on the address bus.
This gives the accessed memory more time to respond to the transaction request.
A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended
number of clock cycles.
6.4 BIU CONTROL REGISTERS
The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be
used for accessing memory. During initialization of the system, these registers should be programmed
with appropriate values so that the minimum allowable number of cycles is used. This number varies with
the clock frequency.
There are five BIU control registers, as listed in Table 6-3. These registers control the bus cycle
configuration used for accessing the various on-chip memory types.
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