CP3BT23_14 Datasheet, PDF (226/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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23 ACCESS.bus Interface
The ACCESS.bus interface module (ACB) is a two-wire serial interface compatible with the ACCESS.bus
physical layer. It permits easy interfacing to a wide range of low-cost memories and I/O devices, including:
EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers. It is
compatible with Intel’s SMBus and Philips’ I2C bus. The ACB module can be configured as a bus master
or slave, and can maintain bidirectional communications with both multiple master and slave devices.
This section presents an overview of the bus protocol, and its implementation by the ACB module.
• ACCESS.bus master and slave
• Supports polling and interrupt-controlled operation
• Generate a wake-up signal on detection of a Start Condition, while in power-down mode
• Optional internal pull-up on SDA and SCL pins
23.1 ACB PROTOCOL OVERVIEW
The ACCESS.bus protocol uses a two-wire interface for bidirectional communication between the devices
connected to the bus. The two interface signals are the Serial Data Line (SDA) and the Serial Clock Line
(SCL). These signals should be connected to the positive supply, through pull-up resistors, to keep the
signals high when the bus is idle.
The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each bus
device has a unique address and can operate as a transmitter or a receiver (though some peripherals are
only receivers).
During data transactions, the master device initiates the transaction, generates the clock signal, and
terminates the transaction. For example, when the ACB initiates a data transaction with an ACCESS.bus
peripheral, the ACB becomes the master. When the peripheral responds and transmits data to the ACB,
their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though
their transmitter/receiver functions are reversed.
23.1.1 Data Transactions
One data bit is transferred during each clock period. Data is sampled during the high phase of the serial
clock (SCL). Consequently, throughout the clock high phase, the data must remain stable (see Figure 23-
1). Any change on the SDA signal during the high phase of the SCL clock and in the middle of a
transaction aborts the current transaction. New data must be driven during the low phase of the SCL
clock. This protocol permits a single data line to transfer both command/control information and data using
the synchronous serial clock.
Figure 23-1. Bit Transfer
Each data transaction is composed of a Start Condition, a number of byte transfers (programmed by
software), and a Stop Condition to terminate the transaction. Each byte is transferred with the most
significant bit first, and after each byte, an Acknowledge signal must follow.
226 ACCESS.bus Interface
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