CP3BT23_14 Datasheet, PDF (203/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
While in Attention mode, the UART receiver monitors the communication flow but ignores all characters
until an address character is received. On receiving an address character, the contents of the receive shift
register are copied to the receive buffer. The URBF bit is set and an interrupt (if enabled) is generated.
The UATN bit is automatically cleared, and the UART begins receiving all subsequent characters.
Software must examine the contents of the URBUF register and respond by accepting the subsequent
characters (by leaving the UATN bit clear) or waiting for the next address character (by setting the UATN
bit again).
The operation of the UART transmitter is not affected by the selection of this mode. The value of the ninth
bit to be transmitted is programmed by setting or clearing the UXB9 bit in the UART Frame Select register.
The value of the ninth bit received is read from URB9 in the UART Status Register.
21.2.4 Diagnostic Mode
The Diagnostic mode is available for testing of the UART. In this mode, the TXD and RXD pins are
internally connected together, and data shifted out of the transmit shift register is immediately transferred
to the receive shift register. This mode supports only the 9-bit data format with no parity. The number of
start and stop bits is programmable.
21.2.5 Frame Format Selection
The format shown in Figure 21-4 consists of a start bit, seven data bits (excluding parity), and one or two
stop bits. If parity bit generation is enabled by setting the UPEN bit, a parity bit is generated and
transmitted following the seven data bits.
Start
1
Bit
7-Bit Data
1S
1a
Start
Bit
7-Bit Data
2S
Start
1b
Bit
7-Bit Data
PA 1S
1c
Start
Bit
7-Bit Data
PA
2S
DS063
Figure 21-4. 7-Bit Data Frame Options
The format shown in Figure 21-5 consists of one start bit, eight data bits (excluding parity), and one or two
stop bits. If parity bit generation is enabled by setting the UPEN bit, a parity bit is generated and
transmitted following the eight data bits.
Start
2
Bit
8-Bit Data
1S
Start
2a
Bit
8-Bit Data
2S
Start
2b
Bit
8-Bit Data
PA 1S
2c
Start
Bit
8-Bit Data
PA 2S
DS064
Figure 21-5. 8-Bit Data Frame Options
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