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CP3BT23_14 Datasheet, PDF (269/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces
CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
26.2.6 Clock Prescaler Register 1 (CLK1PS)
The CLK1PS register is a word-wide read/write register. The register is split into two 8-bit fields called
C1PRSC and C2PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 1
and 2 respectively. The register is cleared at reset.
15
8
7
0
C2PRSC
C1PRSC
C1PRSC
C2PRSC
The Clock Prescaler 1 Compare Value field holds the 8-bit prescaler value for timer
subsystem 1. The counter of timer subsystem is incremented each time when the clock
prescaler compare value matches the value of the clock prescaler counter. The division ratio
is equal to (C1PRSC + 1). For example, 00h is a ratio of 1, and FFh is a ratio of 256.
The Clock Prescaler 2 Compare Value field holds the 8-bit prescaler value for timer
subsystem 2. The counter of timer subsystem is incremented each time when the clock
prescaler compare value matches the value of the clock prescaler counter. The division ratio
is equal to (C2PRSC + 1).
26.2.7 Clock Prescaler Register 2 (CLK2PS)
The Clock Prescaler Register 2 (CLK2PS) is a word-wide read/write register. The register is split into two
8-bit fields called C3PRSC and C4PRSC. Each field holds the 8-bit clock prescaler compare value for
timer subsystems 3 and 4 respectively. The register is cleared at reset.
15
8
7
0
C4PRSC
C3PRSC
C3PRSC
C4PRSC
The Clock Prescaler 3 Compare Value field holds the 8-bit prescaler value for timer
subsystem 3. The counter of timer subsystem is incremented each time when the clock
prescaler compare value matches the value of the clock prescaler counter. The division ratio
is equal to (C3PRSC + 1).
The Clock Prescaler 4 Compare Value field holds the 8-bit prescaler value for timer
subsystem 4. The counter of timer subsystem is incremented each time when the clock
prescaler compare value matches the value of the clock prescaler counter. The division ratio
is equal to (C4PRSC + 1).
26.2.8 Counter Register n (COUNTx)
The Counter (COUNTx) registers are word-wide read/write registers. There are a total of four registers
called COUNT1 through COUNT4, one for each of the four timer subsystems. Software may read the
registers at any time. Reading the register will return the current value of the counter. The register may
only be written if the counter is stopped (i.e. if both TxRUN bits associated with a timer subsystem are
clear). The registers are cleared at reset.
15
0
CNTx
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Versatile Timer Unit (VTU) 269