CP3BT23_14 Datasheet, PDF (291/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
(continued)
(Temperature: –40°C ≤ TA ≤ +85°C)
Symbol
Parameter
Conditions
Min
I_OLTS
Touchscreen Logical 0
Output Current⁽²⁾ (for
V_OL = 0.15V, ADVcc = 2.25V
18
ADC2/TSXand ADC3/TSY–)
I_OHTS
Touchscreen Logical 1
V_OH = 2.1, ADVcc = 2.25V
-18
Output Current⁽²⁾ (for
ADC0/TSX+ and
ADC1/TSY+)
I_OHW
Weak Pull-up Current
V_IL = 0V,
-20
IOVcc = 3.63V
I_L
High Impedance Input
0 V ≤ Vin ≤ IOVcc
-2
Leakage Current⁽³⁾ (except
ADC0/TSX+, ADC1/TSY+,
ADC2/TSX-, ADC3/TSY–)
I_L
High Impedance Input
0 V ≤ Vin ≤ IOVcc
-5
Leakage Current (for
ADC0/TSX+, ADC1/TSY+,
ADC2/TSX–, ADC3/TSY–)
I_O(Off)
Output Leakage Current (I/O 0 V ≤ Vout ≤ Vcc
-2
pins in input mode)
Icca
Digital Supply Current Active Vcc = 2.75V, IOVcc=3.63V
Mode ⁽⁴⁾
Iccprog
Digital Supply Current Active Vcc = 2.75V, IOVcc = 3.63V
Mode ⁽⁵⁾
Iccps
Digital Supply Current Power Vcc = 2.75V, IOVcc =3.63V
Save Mode⁽⁶⁾
Iccid
Digital Supply Current Idle
Mode ⁽⁷⁾
Vcc = 2.75V, IOVcc = 3.63V
Iccq
Digital Supply Current Halt Vcc = 2.75V, IOVcc =
Mode ^{(7) (8)}
3.63V,20°C
Max
-300
2
5
2
20
20
4
2
150
Units
mA
mA
µA
µA
µA
µA
mA
mA
mA
mA
µA
(2) Characterized not tested in production.
(3) Some pins not tested for leakage due to I/O structure.
(4) Run from internal memory (RAM), Iout = 0 mA, X1CKI = 12 MHz, PLL enabled (4×), internal system clock is 24 MHz, not programming
Flash memory
(5) Same conditions as Icca1, but programming or erasing Flash memory page
(6) Running from internal memory (RAM), Iout = 0 mA, XCKI1 = 12 MHz, PLL disabled, X2CKI = 32.768 kHz, device put in power-save
mode, Slow Clock derived from XCKI1
(7) Iout = 0 mA, XCKI1 = Vcc, X2CKI = 32.768 kHz
(8) Halt current approximately doubles for every 20°C.
29.5 ADC ELECTRICAL CHARACTERISTICS
29.6 over operating free-air temperature range (unless otherwise noted)
V_PREF
V_NREF
PARAMETER
ADC Positive Reference Input⁽¹⁾
ADC Negative Reference Input⁽¹⁾
ADC Input Range⁽¹⁾
TEST CONDITIONS
Clock Frequency
t_C
Conversion Time (12-bit result)
INL
Integral Non-Linearity
DNL
C_ADCIN
C_ADCINS
R_ADCIN
Differential Non-Linearity
Total Capacitance of ADC Input⁽¹⁾
Switched Capacitance of ADC
Input ⁽¹⁾
Resistance of ADC Input Path⁽¹⁾
(1) Specified by design
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MIN
2
0
V_NREF
9
8
0.1
TYP
12
14
MAX
2.75
0.25
V_PREF
±2
±0.7
20
10
UNIT
V
V
V
MHz
µs
LSB
LSB
pF
pF
12 kohm
Electrical Characteristics 291