CP3BT23_14 Datasheet, PDF (227/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
At each clock cycle, the slave can stall the master while it handles the previous data, or prepares new
data. This can be performed for each bit transferred or on a byte boundary by the slave holding SCL low
to extend the clock-low period. Typically, slaves extend the first clock cycle of a transfer if a byte read has
not yet been stored, or if the next byte to be transmitted is not yet ready. Some microcontrollers with
limited hardware support for ACCESS.bus extend the access after each bit, to allow software time to
handle this bit.
Start and Stop
The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is
generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition
is generated. A high-tolow transition of the data line (SDA) while the clock (SCL) is high indicates a Start
Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition
(Figure 23-2).
SDA
SCL
S
Start
Condition
P
Stop
Condition
DS076
Figure 23-2. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a
transaction. This allows another device to be accessed, or a change in the direction of the data transfer.
Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each
byte transferred, and the acknowledge signal sent by the receiving device (Figure 23-3).
SDA
SCL
S
1-7 8 9
Address R/W ACK
1-7 8 9
Data
ACK
1-7 8 9
P
Data
AC K
Start
Condition
Stop
Condition
DS079
Figure 23-3. ACCESS.bus Data Transaction
The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The
transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge
signal. The receiver must pull down the SDA line during the acknowledge clock pulse, which signals the
correct reception of the last data byte, and its readiness to receive the next byte. Figure 23-4 illustrates
the acknowledge cycle.
Data Output
by Transmitter
Data Output
by Receiver
Transmitter Stays Off
the Bus During the
Acknowledgment Clock
Acknowledgment
Signal from Receiver
SCL
1 2 3-6 7 8 9
S
Start
Condition
DS078
Figure 23-4. ACCESS.bus Acknowledge Cycle
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ACCESS.bus Interface 227