CP3BT23_14 Datasheet, PDF (256/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
www.ti.com
TCPND
TDPND
TAIEN
TBIEN
TCIEN
TDIEN
The Timer Interrupt Source C Pending bit indicates that timer interrupt condition C has
occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 25-1. This bit
can be set by hardware or by software. To clear this bit, software must use the Timer
Interrupt Clear Register (TICLR). Attempting to directly write a 0 to this bit is ignored.
0 – Interrupt source C has not triggered.
1 – Interrupt source C has triggered.
The Timer Interrupt Source D Pending bit indicates that timer interrupt condition D has
occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 25-1. This bit
can be set by hardware or by software. To clear this bit, software must use the Timer
Interrupt Clear Register (TICLR). Attempting to directly write a 0 to this bit is ignored.
0 – Interrupt source D has not triggered.
1 – Interrupt source D has triggered.
The Timer Interrupt A Enable bit controls whether an interrupt is generated on each
occurrence of interrupt condition A. For an explanation of interrupt conditions A, B, C, and D,
see Table 25-1.
0 – Condition A interrupts disabled.
1 – Condition A interrupts enabled.
The Timer Interrupt B Enable bit controls whether an interrupt is generated on each
occurrence of interrupt condition B. For an explanation of interrupt conditions A, B, C, and D,
see Table 25-1.
0 – Condition B interrupts disabled.
1 – Condition B interrupts enabled.
The Timer Interrupt C Enable bit controls whether an interrupt is generated on each
occurrence of interrupt condition C. For an explanation of interrupt conditions A, B, C, and D,
see Table 25-1.
0 – Condition C interrupts disabled.
1 – Condition C interrupts enabled.
The Timer Interrupt D Enable bit controls whether an interrupt is generated on each
occurrence of interrupt condition D. For an explanation of interrupt conditions A, B, C, and D,
see Table 25-1.
0 – Condition D interrupts disabled.
1 – Condition D interrupts enabled.
25.5.9 Timer Interrupt Clear Register (TICLR)
The TICLR register is a byte-wide, write-only register that allows software to clear the TAPND, TBPND,
TCPND, and TDPND bits in the Timer Interrupt Control (TICTRL) register. Do not modify this register with
instructions that access the register as a read-modify-write operand, such as the bit manipulation
instructions. The register reads as FFh. The register format is shown below.
7
4
3
2
1
0
Reserved
TDCLR
TCCLR
TBCLR
TACLR
TACLR
TBCLR
The Timer Pending A Clear bit is used to clear the Timer Interrupt Source A Pending bit
(TAPND) in the Timer Interrupt Control register (TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TAPND bit.
The Timer Pending A Clear bit is used to clear the Timer Interrupt Source B Pending bit
(TBPND) in the Timer Interrupt Control register (TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TBPND bit.
256 Multi-Function Timer
Submit Documentation Feedback
Product Folder Links: CP3BT23
Copyright © 2013–2014, Texas Instruments Incorporated