CP3BT23_14 Datasheet, PDF (224/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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EIR
EIW
SCM
SCIDL
SCDV
The Enable Interrupt for Read bit controls whether an interrupt is generated when the read
buffer becomes full. When set, an interrupt is generated when the Read Buffer Full bit
(MWSTAT.RBF) is set. Otherwise, no interrupt is generated when the read buffer is full.
0 – No read buffer full interrupt.
1 – Interrupt when read buffer becomes full.
The Enable Interrupt for Write bit controls whether an interrupt is generated when the Busy
bit (MWSTAT.BSY) is cleared, which indicates that a data transfer sequence has been
completed and the read buffer is ready to receive the new data. Otherwise, no interrupt is
generated when the Busy bit is cleared.
0 – No interrupt on data transfer complete.
1 – Interrupt on data transfer complete.
The Shift Clock Mode bit selects between the normal clocking mode and the alternate
clocking mode. In the normal mode, the output data is clocked out on the falling edge of MSK
and the input data is sampled on the rising edge of MSK. In the alternate mode, the output
data is clocked out on the rising edge of MSK and the input data is sampled on the falling
edge of MSK.
0 – Normal clocking mode.
1 – Alternate clocking mode.
The Shift Clock Idle bit controls the value of the MSK output when the Microwire module is
idle. This bit must be changed only when the Microwire module is disabled (MEN = 0) or
when no bus transaction is in progress (MWSTAT.BSY = 0).
0 – MSK is low when idle.
1 – MSK is high when idle
The Shift Clock Divider Value field specifies the divisor used for generating the MSK shift
clock from the System Clock. The divisor is 2 × (SCDV[6:0] + 1). Valid values are 0000001b
to 1111111b, so the division ratio may range from 3 to 256. This field is ignored in slave
mode (MWCTL1.MNS=0).
22.5.3 Microwire Status Register (MWSTAT)
The MWSTAT register is a word-wide, read-only register that shows the current status of the Microwire
interface module. At reset, all non-reserved bits are clear. The register format is shown below.
15
Reserved
3
2
1
0
OVR
RBF
BSY
BSY
The Busy bit, when set, indicates that the Microwire shifter is busy. In master mode, the BSY
bit is set when the MWDAT register is written. In slave mode, the bit is set on the first leading
edge of MSK when MWCS is asserted or when the MWDAT register is written, whichever
occurs first. In both master and slave modes, this bit is cleared when the Microwire data
transfer sequence is completed and the read buffer is ready to receive the new data; in other
words, when the previous data held in the read buffer has already been read. If the previous
data in the read buffer has not been read and new data has been received into the shift
register, the BSY bit will not be cleared, as the transfer could not be completed because the
contents of the shift register could not be transferred into the read buffer.
0 – Microwire shifter is not busy.
1 – Microwire shifter is busy.
224 Microwire/SPI Interface
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