CP3BT23_14 Datasheet, PDF (165/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
18.11.2 Transceiver Connection
An external transceiver chip must be connected between the CAN block and the bus. It establishes a bus
connection in differential mode and provides the driver and protection requirements. Figure 18-31 shows a
possible ISO-High-Speed configuration.
120
Termination
APB Bus
CAN
Interface
CANRX
CANTX
Transceiver Chip
REF
RX
TX
RS
VCC
BUS_H
BUS_L
GND
VCC
CAN bus
signals
To other
modules
120
DS464
Figure 18-31. External Transceiver
18.11.3 Timing Requirements
Processing messages and updating message buffers require a certain number of clock cycles, as shown
in Table 18-22. These requirements may lead to some restrictions regarding the Bit Time Logic settings
and the overall CAN performance which are described below in more detail. Wait cycles need to be added
to the cycle count for CPU access to the object memory as described in Section 18.9.1. The number of
occurrences per frame is dependent on the number of matching identifiers.
Table 18-22. CAN Module Internal Timing
Task
Copy hidden buffer to receive message buffer
Update status from TX_RTR to TX_ONCE_RTR
Schedule a message for transmission
Cycle Count
17
3
2
Occurrence/ Frame
0-1
0-15
0-1
The critical path derives from receiving a remote frame, which triggers the transmission of one or more
data frames. There are a minimum of four bit times in-between two consecutive frames. These bit times
start at the validation point of received frame (reception of 6th EOF bit) and end at the earliest possible
transmission start of the next frame, which is after the third intermission bit at 100% burst bus load.
These four bit times have to be set in perspective with the timing requirements of the CAN module.
The minimum duration of the four CAN bit times is determined by the following Bit Time Logic settings:
PSC = PSCmin = 2
TSEG1 = TSEG1min = 2
TSEG2 = TSEG2min = 1
Bit time = Sync + Time Segment 1 + Time Segment 2
= (1 + 2 + 1) tq = 4 tq
= (4 tq × PSC) clock cycles
= (4 tq × 2) clock cycles = 8 clock cycles
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CAN Module 165